[Intel-gfx] [PATCH 2/4]Use ?best PLL timing values for G4X chipset

[Wang, Zhenyu Z]

On 2009.03.13 13:23:38 +0800, Ma, Ling wrote:
> > > @@ -581,21 +595,20 @@ i830FindBestPLL(xf86CrtcPtr crtc, int target, int refclk, intel_clock_t *best_cl
> > >  
> > >      memset (best_clock, 0, sizeof (*best_clock));
> > >  
> > > -    for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) 
> > > +    for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++)
> > >      {
> > > -	for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++)
> > > +	for (clock.m2 = limit->m2.min;
> > > +		clock.m2 < clock.m1 && clock.m2 <= limit->m2.max; clock.m2++)
> > >  	{
> > > -	    /* m1 is always 0 in IGD */
> > > -	    if (clock.m2 >= clock.m1 && !IS_IGD(pI830))
> > > -		break;
> > 
> > This's wrong to me, it will break on IS_IGD. As m1 is always 0, you filter
> > out all possbile m2. Could you keep origin pll find function unchanged in this
> > patch? If there's other fix, that should be in another patch, and also split
> > white space clean patch.
> oh, yes, but because M1 in 8xx and 9xx platform is always above M2, I
> prefer the code like below.  
> for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++)
> {
>  -	    /* m1 is always 0 in IGD */
>  -	    if (clock.m2 >= clock.m1 && !IS_IGD(pI830))
>  -		break;
> don't need "break" action. 

break will save some extending loops right?

> > Could you have a comment block for pll generation algorithm on G4x?
> > like 
> > /* 
> >  *  G4X PLL generation criteria:
> >  *  - prefer smaller n
> >  *  - prefer larger m1, m2, p1
> >  *  - precision override m1,m2,p1
> >  *  - N override precision
> >  */
> > 
> we have appended comments before each action.

Last two points are copied from Michael's mail, put it together seems more clear.


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