[Intel-gfx] PATCH 0/2]drm/i915: find best pll seting sync up with 2D driver

[Ma Ling]

Hi Eric
The patches for 2D driver has fixed bug #17508 and #17805
Any more comments or we can merge it into our tree? 

Thanks 
Ma Ling

On Tue, 2009-03-10 at 21:00 +0800, Ma Ling wrote:
> Hi Eric,
> 
> this is latest patches for pll.
> 
> [PATCH 1/2]drm/i915: Define documented PLL timing limits for G4X
> chipsets. 
> [PATCH 2/2]drm/i915: Use best PLL timing values for G4X chipsets.
> 
> Thanks
> Ma Ling