[Intel-gfx] [PATCH] drm/i915: allocate fences for 965+ pins also

[Jesse Barnes]

Current userspace doesn't use GTT mapping & faulting, so it won't have fences installed correctly on 965+ chips, so make sure that happens.

Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_gem.c |    8 ++------
 1 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index aab5fa2..57eeb36 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2772,12 +2772,8 @@ i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
 			return ret;
 		}
 	}
-	/*
-	 * Pre-965 chips need a fence register set up in order to
-	 * properly handle tiled surfaces.
-	 */
-	if (!IS_I965G(dev) &&
-	    obj_priv->fence_reg == I915_FENCE_REG_NONE &&
+
+	if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
 	    obj_priv->tiling_mode != I915_TILING_NONE) {
 		ret = i915_gem_object_get_fence_reg(obj, true);
 		if (ret != 0) {
-- 
1.5.6.3