[Intel-gfx] [PATCH 0/2]drm/i915: Find best PLL timing to obtain stable image on G4X platform(V3)

[Eric Anholt]

On Wed, 2009-03-18 at 20:13 +0800, Ma Ling wrote:
> Our clock is generated by parameters- n, m1, m2, p1, p2. However for
> different platforms we need corresponding setting parameters so that
> clock derived from them matches hardware requirement. The patch intends
> to provide precise parameters specified in reference spreadsheet.
> It has fixed bug #17805 and #17508.

Applied to for-linus, thanks.  (And thanks for sticking through all
these review cycles :) )

-- 
Eric Anholt
eric at anholt.net                         eric.anholt at intel.com


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