[Intel-gfx] [PATCH] drm/i915: allocate fences for 965+ pins also

[Jesse Barnes]

On Fri, 20 Mar 2009 14:35:30 -0700
Eric Anholt <eric at anholt.net> wrote:

> On Fri, 2009-03-20 at 14:16 -0700, Jesse Barnes wrote:
> > Current userspace doesn't use GTT mapping & faulting, so it won't
> > have fences installed correctly on 965+ chips, so make sure that
> > happens.
> 
> So now the pinning that happens for execbuf will suck up fence
> registers?  Fail.
> 
> Could we just do the 965 stuff in the ioctl?

Well another option would be to just use the GTT mapping stuff in the
2D driver (in fact I'd prefer that); that *will* install a fence reg at
fault time. Only faulting is broken due to PAT lolz atm...

-- 
Jesse Barnes, Intel Open Source Technology Center