[Intel-gfx] [PATCH 2/2] drm/i915: Restore the DPLL calculation logic for 9xx platform

[Daniele C.]

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yakui.zhao at intel.com ha scritto:
> From: Zhao Yakui <yakui.zhao at intel.com>
> 
> The DPLL calculation logic for 9xx platform is changed in the following commit:
>     >commit 652c393a3368af84359da37c45afc35a91144960
> Author: Jesse Barnes <jbarnes at virtuousgeek.org>
> Date:   Mon Aug 17 13:31:43 2009 -0700
> 
>     drm/i915: add dynamic clock frequency control
> 
> So restore the DPLL calculation logic for 9xx platform.
> 
> Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   21 +++++++++++----------
>  1 files changed, 11 insertions(+), 10 deletions(-)


Might these 2 patchset for DRM/i915 might some improvement related to bugs [1] and [2]?
Are they merged to some kernel GIT repository already ([3])?

[1] http://bugs.freedesktop.org/show_bug.cgi?id=24789
[2] http://bugs.freedesktop.org/show_bug.cgi?id=12882
[3] http://git.kernel.org/

Thanks,
- --
  Daniele C.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/

iQEcBAEBAgAGBQJLAqiMAAoJEON28As9epPAKZEH/Rcb45yACyYe5SaPJSWKfkFs
DSm7OhQppm4r0G33KJz4CIVhYTs/LX63szl1PKAxOKn+N36xUO/SxyWfC76ekTpU
2U7IqmZDMK+xdv6rpmSYsn9GIs+rmJ7SMyrwW79JYZQKL26JEoeBQG6KqqbncND6
dN7BT0Sbg5oR2yqWHjR3zK5SxtX3pYLV2SjQP15uFevFWa0IKDXMWPvXKbZGkTqa
seTTi6dF9XvlGNVyFM/1e+MoNqv/bY09YCrbdPA2ASVRQAWylOdN46qSw7crsvFg
CpFqmLRSL9mZYTN3o2wP4lqI5nQKoTOn7bxeJ3HxkTwGbpmXvI1HmYe2KBnxkC4=
=3SDG
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