[Intel-gfx] [PATCH] disable FBC for IGD

[Shaohua Li]

IGD doesn't support FBC. Enabling it will cause boot hang.

Signed-off-by: Shaohua Li <shaohua.li at intel.com>

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 45d507e..6c26bd6 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1228,7 +1228,7 @@ static int i915_load_modeset_init(struct drm_device *dev,
 
 	/* Try to set up FBC with a reasonable compressed buffer size */
 	if (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev) || IS_GM45(dev)) &&
-	    i915_powersave) {
+	    !IS_IGD(dev) && i915_powersave) {
 		int cfb_size;
 
 		/* Try to get an 8M buffer... */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b24b2d1..8746c42 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -979,7 +979,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 
 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
 #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
-#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev)))
+#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev)) && !IS_IGD(dev))
 
 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)