[Intel-gfx] Framebuffer compression with 2.6.32-rc

Florian Mickler florian at mickler.org
Thu Oct 15 12:41:09 CEST 2009

On Wed, 14 Oct 2009 15:24:37 -0700
Jesse Barnes <jbarnes at virtuousgeek.org> wrote:

> It should be checking the enable bit instead, the compressing bit will
> be turning on & off a lot.
> But we have a register dumper for this, so I don't think we need a
> debugfs file...

On Thu, 15 Oct 2009 07:06:50 +0200
Tino Keitel <tino.keitel+xorg at tikei.de> wrote:
> I already asked, but no reply yet: how do I actually use this register
> dumper, and how do I see if FBC is enabled?
> Regards,
> Tino

hm... good question... i get this:

# ./intel_reg_dumper  | grep FBC
(II):         FBC_CFB_BASE: 0x7f800000
(II):          FBC_LL_BASE: 0x7e082000
(II):          FBC_CONTROL: 0x00000000
(II):          FBC_COMMAND: 0x00000000
(II):           FBC_STATUS: 0x20000000
(II):         FBC_CONTROL2: 0x00000000
(II):        FBC_FENCE_OFF: 0x00000000
(II):          FBC_MOD_NUM: 0x00000000

looking in drivers/gpu/drm/i915/i915_reg.h i only see one enable bit
regarding fbc and it is in the control register 
(  #define   FBC_CTL_EN            (1<<31) ) 

as FBC_CONTROL is 0x0 i'm pretty shure in my case it is off.. ? 


p.s. is this in the intel hardware manuals?

A: Because it messes up the order in which people normally read text.
> Q: Why is top-posting such a bad thing?  
>> A: Top-posting.  
>>> Q: What is the most annoying thing in e-mail?
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