[Intel-gfx] [PATCH] drm/i915: enable self-refresh on 965

[ykzhao]

On Tue, 2009-10-20 at 06:49 +0800, Jesse Barnes wrote:
> From 4744d54c2cf813ebda8e4362c4361d13edf3cac0 Mon Sep 17 00:00:00 2001
> From: Jesse Barnes <jbarnes at jbarnes-x200.(none)>
> Date: Mon, 19 Oct 2009 10:08:17 +0900
> Subject: [PATCH 1/3] drm/i915: enable self-refresh on 965
> 
> Need to calculate the SR watermark and enable it.
> 
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    1 +
>  drivers/gpu/drm/i915/intel_display.c |   31 +++++++++++++++++++++++++++----
>  2 files changed, 28 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0466ddb..0bdd711 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1790,6 +1790,7 @@
>  #define   DSPARB_AEND_SHIFT	0
>  
>  #define DSPFW1			0x70034
> +#define   DSPFW_SR_SHIFT	23
>  #define DSPFW2			0x70038
>  #define DSPFW3			0x7003c
>  #define   IGD_SELF_REFRESH_EN	(1<<30)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a0f6bbe..7a18cbb 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2445,15 +2445,38 @@ static void g4x_update_wm(struct drm_device *dev, int unused, int unused2,
>  	I915_WRITE(FW_BLC_SELF, fw_blc_self);
>  }
>  
> -static void i965_update_wm(struct drm_device *dev, int unused, int unused2,
> -			   int unused3, int unused4)
> +static void i965_update_wm(struct drm_device *dev, int planea_clock,
> +			   int planeb_clock, int sr_hdisplay, int pixel_size)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> +	unsigned long line_time_us;
> +	int sr_clock, sr_entries, srwm = 1;
> +
> +	/* Calc sr entries for one plane configs */
> +	if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
> +		/* self-refresh has much higher latency */
> +		const static int sr_latency_ns = 12000;
> +
> +		sr_clock = planea_clock ? planea_clock : planeb_clock;
> +		line_time_us = ((sr_hdisplay * 1000) / sr_clock);
> +
> +		/* Use ns/us then divide to preserve precision */
> +		sr_entries = (((sr_latency_ns / line_time_us) + 1) *
> +			      pixel_size * sr_hdisplay) / 1000;
> +		sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
> +		DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
> +		srwm = I945_FIFO_SIZE - sr_entries;
> +		if (srwm < 0)
> +			srwm = 1;
> +		srwm &= 0x3f;
> +		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
> +	}

Will you please use the DRM_DEBUG_KMS instead of DRM_DEBUG?
Thanks.
> -	DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
> +	DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", srwm);
>  
>  	/* 965 has limitations... */
> -	I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
> +	I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
> +		   (8 << 0));
>  	I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
>  }
>