[Intel-gfx] [PATCH] drm/i915/pch: Use minimal number of FDI lanes

Zhenyu Wang zhenyuw at linux.intel.com
Mon Apr 12 11:03:24 CEST 2010

On 2010.04.09 17:55:10 -0400, Adam Jackson wrote:
> This should be a small power savings, but the Watts-Up I used to test is
> only precise to within 100mW.  Tested on Lenovo T410 (Ironlake), LVDS
> VGA and DisplayPort, up to 1920x1200R.
> Signed-off-by: Adam Jackson <ajax at redhat.com>

Nice work for per crtc FDI lane config! We might have some limit on future
hw for FDI lane number, in consider of the introduction with the third pipe,
but this one is true for all current systems.

Adam, this should be a d-i-n patch right? I've changed FDI link setting for
Sandybridge on that branch, so please rebase onto that. This should also apply
true for SNB/CPT system, I'll give it a testing.

Acked-by: Zhenyu Wang <zhenyuw at linux.intel.com>


Open Source Technology Center, Intel ltd.

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