[Intel-gfx] [PATCH] drm/i915/pch: Use minimal number of FDI lanes

[ykzhao]

On Sat, 2010-04-10 at 05:55 +0800, Adam Jackson wrote:
> This should be a small power savings, but the Watts-Up I used to test is
> only precise to within 100mW.  Tested on Lenovo T410 (Ironlake), LVDS
> VGA and DisplayPort, up to 1920x1200R.

Very good point.

I test this patch on another laptop. Only when LVDS is used, it seems
that it can save about 0.2W idle power. 

thanks
    yakui  
> 
> Signed-off-by: Adam Jackson <ajax at redhat.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   23 ++++++++++++++++++-----
>  drivers/gpu/drm/i915/intel_drv.h     |    1 +
>  2 files changed, 19 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index eb4a265..39b77d0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1582,9 +1582,10 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
>  			 */
>  			temp &= ~(0x7 << 16);
>  			temp |= (pipe_bpc << 11);
> +			temp &= ~(7 << 19);
> +			temp |= (intel_crtc->fdi_lanes - 1) << 19;
>  			I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
> -					FDI_SEL_PCDCLK |
> -					FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
> +					FDI_SEL_PCDCLK);
>  			I915_READ(fdi_rx_reg);
>  			udelay(200);
>  
> @@ -1630,7 +1631,8 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
>  			/* enable CPU FDI TX and PCH FDI RX */
>  			temp = I915_READ(fdi_tx_reg);
>  			temp |= FDI_TX_ENABLE;
> -			temp |= FDI_DP_PORT_WIDTH_X4; /* default */
> +			temp &= ~(7 << 19);
> +			temp |= (intel_crtc->fdi_lanes - 1) << 19;
>  			temp &= ~FDI_LINK_TRAIN_NONE;
>  			temp |= FDI_LINK_TRAIN_PATTERN_1;
>  			I915_WRITE(fdi_tx_reg, temp);
> @@ -3043,7 +3045,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
>  
>  	/* FDI link */
>  	if (HAS_PCH_SPLIT(dev)) {
> -		int lane, link_bw, bpp;
> +		int lane = 0, link_bw, bpp;
>  		/* eDP doesn't require FDI link, so just set DP M/N
>  		   according to current link config */
>  		if (is_edp) {
> @@ -3059,7 +3061,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
>  				target_clock = mode->clock;
>  			else
>  				target_clock = adjusted_mode->clock;
> -			lane = 4;
>  			link_bw = 270000;
>  		}
>  
> @@ -3111,6 +3112,18 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
>  			bpp = 24;
>  		}
>  
> +		if (!lane) {
> +			/* 
> +			 * Account for spread spectrum to avoid
> +			 * oversubscribing the link. Max center spread
> +			 * is 2.5%; use 5% for safety's sake.
> +			 */
> +			u32 bps = target_clock * bpp * 19 / 20;
> +			lane = bps / (link_bw * 8) + 1;
> +		}
> +
> +		intel_crtc->fdi_lanes = lane;
> +
>  		ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index c15ec47..d716f35 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -154,6 +154,7 @@ struct intel_crtc {
>  	bool lowfreq_avail;
>  	struct intel_overlay *overlay;
>  	struct intel_unpin_work *unpin_work;
> +	int fdi_lanes;
>  };
>  
>  #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)