[Intel-gfx] [PATCH] drm/i915: remove unnecessary PIPE_CONTROL cache flushing

[Jesse Barnes]

Was better safe than sorry, but it appears these bits aren't necessary.

Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_gem.c |    5 +----
 1 files changed, 1 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 56ff905..5a34b71 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1637,8 +1637,7 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
 		 * an interrupt.
 		 */
 		BEGIN_LP_RING(32);
-		OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
-			 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
+		OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE);
 		OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
 		OUT_RING(seqno);
 		OUT_RING(0);
@@ -1654,7 +1653,6 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
 		scratch_addr += 128;
 		PIPE_CONTROL_FLUSH(scratch_addr);
 		OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
-			 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
 			 PIPE_CONTROL_NOTIFY);
 		OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
 		OUT_RING(seqno);
@@ -1664,7 +1662,6 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
 		/* Don't penalize non-ilk parts with the extra writes */
 		BEGIN_LP_RING(4);
 		OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
-			 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
 			 PIPE_CONTROL_NOTIFY);
 		OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
 		OUT_RING(seqno);
-- 
1.7.0.1