[Intel-gfx] [PATCH] drm/i915: Enable aspect/centering panel fitting for Ironlake.

[Chris Wilson]

On Thu, 5 Aug 2010 09:11:26 +0800, Zhenyu Wang <zhenyuw at linux.intel.com> wrote:
> On 2010.08.04 15:04:01 +0100, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 07f893f..9b5fab4 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1914,15 +1914,13 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
> >  		/* Enable panel fitting for LVDS */
> >  		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
> >  		    || HAS_eDP || intel_pch_has_edp(crtc)) {
> > -			temp = I915_READ(pf_ctl_reg);
> > -			I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
> > -
> > -			/* currently full aspect */
> > -			I915_WRITE(pf_win_pos, 0);
> > -
> > -			I915_WRITE(pf_win_size,
> > -				   (dev_priv->panel_fixed_mode->hdisplay << 16) |
> > -				   (dev_priv->panel_fixed_mode->vdisplay));
> > +			if (dev_priv->pch_pf_size) {
> > +				temp = I915_READ(pf_ctl_reg);
> > +				I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
> > +				I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos);
> > +				I915_WRITE(pf_win_size, dev_priv->pch_pf_size);
> > +			} else
> > +				I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
> >  		}
> 
> So this breaks panel fitting setting on eDP...

Please illuminate the poor ignorant fool (that's me) what the requirements
for eDP are. Even better in patch form. ;-)

Does eDP require panel fitting always?
-- 
Chris Wilson, Intel Open Source Technology Centre