[Intel-gfx] [PATCH 2/4] agp/intel: Fix cache control for Sandybridge

[Eric Anholt]

On Thu, 19 Aug 2010 09:46:14 +0800, Zhenyu Wang <zhenyuw at linux.intel.com> wrote:
> Sandybridge GTT has new cache control bits in PTE, which controls
> graphics page cache in LLC or LLC/MLC. This one trys to setup a
> new gtt driver for Gen6, and using new type mask function for that.
> And this sets cache control to always LLC only by default on Gen6.
> 
> As this gtt memory cache control bits are internal to intel hw,
> so I don't add new flags in agp_backend.h but add them only in
> intel_gtt.c. So drm/i915 stuff needs to know these new flags too.
> 
> Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
> ---
>  drivers/char/agp/intel-gtt.c    |   57 ++++++++++++++++++++++++++++++++-------
>  drivers/gpu/drm/i915/i915_drv.h |   11 +++++++
>  2 files changed, 58 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> index d22ffb8..a2ace23 100644
> --- a/drivers/char/agp/intel-gtt.c
> +++ b/drivers/char/agp/intel-gtt.c
> @@ -49,6 +49,33 @@ static struct gatt_mask intel_i810_masks[] =
>  	 .type = INTEL_AGP_CACHED_MEMORY}
>  };

> +/* Don't try to pollute agp_backend.h...
> + * AGP_USER_CACHED_MEMORY default to LLC only */
> +#define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2)
> +#define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4)
> +/* bit flag for GFDT type */
> +#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)

> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 047cd7c..7eee482 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1236,4 +1236,15 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove
>  
>  #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
>  
> +/* Intel specific agp_memory type for Gen6,
> + * must be same as in intel_gtt.c */
> +
> +/* GEN6: memory only cached in LLC, no MLC. As default we always make
> + * memory cached in LLC. */
> +
> +#define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2)
> +#define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4)
> +/* GFDT bit flag */
> +#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)

I complained about it last time, and I'll complain about it again.
Defining this interface in two different files is bogus.  Put it in some
shared header somewhere.  We want more interaction between agp and drm
anyway, time to stop pretending they talk through some general
interface.

I'd go with intel-agp.h, but some of those register defs in there will
probably conflict.  Maybe move those to intel-agp-reg.h?  I don't know.
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