[Intel-gfx] [PATCH] i915: Modify for pineview clock source

[bfreed at chromium.org]

The i915 driver normally assumes the video bios has configured several 
of the LVDS panel registers, and it just inherits the values. If the 
vbios has not run, several of these will need to be setup. 

intel_bios.c: default clock source selection on pineview to use the SSC source.

If these are not correct then although the panel looks ok, output from an HDMI
encoder (eg, Chrontel CH7036) will be incorrect. 

Signed-off-by: Mark Hayter <mdhayter at chromium.org>

Index: drivers/gpu/drm/i915/intel_bios.c
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 943bbad066af79d6fc62891014f15479213aa34e..e2f3629b46a028077aee214bbc323a1b3ca9ca8f 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -506,6 +506,14 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
 	dev_priv->int_tv_support = 1;
 	dev_priv->int_crt_support = 1;
 
+	if (IS_PINEVIEW(dev_priv->dev)) {
+		/* On Pineview flip default to use SSC (VBT can override) */
+		dev_priv->lvds_use_ssc = 1;
+		/* The ssc pin gets 100MHz downspread from timing gen */
+		dev_priv->lvds_ssc_freq = 100;
+	} else {
+		dev_priv->lvds_use_ssc = 0;
+	}
 	/* Set the Panel Power On/Off timings if uninitialized. */
 	if ((I915_READ(PP_ON_DELAYS) == 0) && (I915_READ(PP_OFF_DELAYS) == 0)) {
 		/* Set T2 to 40ms and T5 to 200ms */