[Intel-gfx] [PATCH 01/11] drm/i915: flush CPU wc cache when flushing GTT write domain

[Daniel Vetter]

On Tue, Jan 26, 2010 at 09:30:34AM -0800, Eric Anholt wrote:
> So, it looks like this series isn't required.

You're right. I've rechecked my overlay code and dropping that register
read to flush the wc cache doesn't hang the box when stress-testing
anymore. Dunno what bug I've tried to paper over with this, but it seems
to be gone.

As requested by Chris, I'll resend my patch queue with the wc stuff
dropped.

-Daniel
-- 
Daniel Vetter
Mail: daniel at ffwll.ch
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