[Intel-gfx] Intel Arrandale IGDNG VGA issue

[Zhenyu Wang]

On 2010.02.01 09:15:06 +0800, Zhenyu Wang wrote:
> On 2010.01.29 17:04:38 +0800, Zhenyu Wang wrote:
> > From d4d565de0f0ad8443c3b2a2a18fa20ee9f840bec Mon Sep 17 00:00:00 2001
> > From: Zhenyu Wang <zhenyuw at linux.intel.com>
> > Date: Fri, 29 Jan 2010 16:58:42 +0800
> > Subject: [PATCH] drm/i915: Rework DPLL calculation parameters for Ironlake
> > 
> > Got Ironlake DPLL parameter table, which reflects the hardware
> > optimized values. So this one trys to list DPLL parameters for
> > different output types, should potential fix clock issue seen
> > on new Arrandale CPUs.
> > 
> > Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
> > ---
> 
> Eric, please queue this one up for .33 kernel, that fixed dual channel LVDS
> mode at 1920x1080. And I've done regression testing on CRT/HDMI/DP which is fine.
> 

oh, looks I always assumed 100Mhz for LVDS with SSC, which might be always true.
We might just need to split single/dual channel LVDS, as with SSC the clock
range is mostly same and we could choose a larger one. I would refresh the patch
or Yakui has already beat me on this.

-- 
Open Source Technology Center, Intel ltd.

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