[Intel-gfx] [PATCH] drm/i915: Rework DPLL calculation parameters for Ironlake

[Eric Anholt]

On Thu,  4 Feb 2010 16:59:24 +0800, Zhenyu Wang <zhenyuw at linux.intel.com> wrote:
> Got Ironlake DPLL parameter table, which reflects the hardware
> optimized values. So this one trys to list DPLL parameters for
> different output types, should potential fix clock issue seen
> on new Arrandale CPUs.

Can I get some sort of note, either in the commit message or below it,
of what it's been tested on?  What would a "potential clock issue" be
that's getting fixed?
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