[Intel-gfx] [PATCH 00/13] RFC: pipelined fencing

[Daniel Vetter]

Hi all,

This patch series implements pipelined fence register setup. In other
words, _every_ batchbuffer can use all available fences (save scanout and
pinned, of course) without any stalls (i.e. i915_wait_request calls).

First part (1-8) is mostly cleanups - I was fed up with threading around
seqno's. The rest is the actual implementation, hopefully sensibly split
up.

This applies on top of my recent cleanup&fixlets patch pile.

Comments, test results, anything else, higly welcome. I haven't yet done
any serious benchmarking 'cause current userspace is way too conservative
with tiled buffer usage to really push it (even on my i855). But it seems
to survive composited desktop usage just fine.

Yours, Daniel

Daniel Vetter (13):
  drm/i915: move fence lru to struct drm_i915_fence_reg
  drm/i915: allow lazy emitting of requests
  drm/i915: move flushing list processing to i915_gem_flush
  drm/i915: one request per batchbuffer is enough
  drm/i915: move flushing list processing to i915_retire_commands
  drm/i915: move the wait_rendering call into flush_gpu_write_domain
  drm/i915: kill an no longer necessary BUG_ON
  drm/i915: drop seqno argument from i915_gem_object_move_to_active
  drm/i915: track gpu fence usage more precisely
  drm/i915: prevent unnecessary fence related cpu stalls
  drm/i915: pipelined fencing, part 1: fence stealing
  drm/i915: infrastructure to track pipelined fence setup
  drm/i915: pipelined fencing, part 2: fence setup

 drivers/gpu/drm/i915/i915_drv.h        |   60 ++++---
 drivers/gpu/drm/i915/i915_gem.c        |  305 ++++++++++++++++++++------------
 drivers/gpu/drm/i915/i915_gem_tiling.c |    2 +-
 drivers/gpu/drm/i915/intel_display.c   |    4 +-
 drivers/gpu/drm/i915/intel_overlay.c   |   17 +-
 5 files changed, 240 insertions(+), 148 deletions(-)