[Intel-gfx] [PATCH 10/13] drm/i915: prevent unnecessary fence related cpu stalls

[Daniel Vetter]

Now that we precisely track whether the gpu actually needs a fence,
use it!

Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem.c |    7 +------
 1 files changed, 1 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9af6e9c..83c7d58 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2597,7 +2597,6 @@ i915_gem_clear_fence_reg(struct drm_gem_object *obj)
 int
 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
 {
-	struct drm_device *dev = obj->dev;
 	struct drm_i915_gem_object *obj_priv = obj->driver_private;
 
 	if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
@@ -2609,11 +2608,7 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
 	 */
 	i915_gem_release_mmap(obj);
 
-	/* On the i915, GPU access to tiled buffers is via a fence,
-	 * therefore we must wait for any outstanding access to complete
-	 * before clearing the fence.
-	 */
-	if (!IS_I965G(dev)) {
+	if (obj_priv->fenced_gpu_access) {
 		int ret;
 
 		ret = i915_gem_object_flush_gpu_write_domain(obj, 0);
-- 
1.6.6.1