[Intel-gfx] [PATCH 2/3] drm/i915: Make the BPC in FDI rx/transcoder be consistent with that in pipeconf on Ironlake

[Zhenyu Wang]

On 2010.01.04 16:29:31 +0800, yakui.zhao at intel.com wrote:
> From: Zhao Yakui <yakui.zhao at intel.com>
> 
> Make the BPC in FDI rx/transcoder be consistent with that in pipeconf on Ironlake.
> 
> Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   26 +++++++++++++++++++++++++-
>  1 files changed, 25 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7784e52..31df26c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1493,6 +1493,10 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
>  	int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
>  	u32 temp;
>  	int tries = 5, j, n;
> +	u32 pipe_bpc;
> +
> +	temp = I915_READ(pipeconf_reg);
> +	pipe_bpc = temp & PIPE_BPC_MASK;
>  
>  	/* XXX: When our outputs are all unaware of DPMS modes other than off
>  	 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
> @@ -1524,6 +1528,12 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
>  
>  			/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
>  			temp = I915_READ(fdi_rx_reg);
> +			/*
> +			 * make the BPC in FDI Rx be consistent with that in
> +			 * pipeconf reg.
> +			 */
> +			temp &= ~(0x7 << 16);

Better to define a BPC_MASK for FDI Rx as well.

> +			temp |= (pipe_bpc << 11);
>  			I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
>  					FDI_SEL_PCDCLK |
>  					FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
> @@ -1666,6 +1676,12 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
>  
>  			/* enable PCH transcoder */
>  			temp = I915_READ(transconf_reg);
> +			/*
> +			 * make the BPC in transcoder be consistent with
> +			 * that in pipeconf reg.
> +			 */
> +			temp &= ~PIPE_BPC_MASK;
> +			temp |= pipe_bpc;
>  			I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
>  			I915_READ(transconf_reg);
>  
> @@ -1745,6 +1761,9 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
>  		I915_READ(fdi_tx_reg);
>  
>  		temp = I915_READ(fdi_rx_reg);
> +		/* BPC in FDI rx is consistent with that in pipeconf */
> +		temp &= ~(0x07 << 16);
> +		temp |= (pipe_bpc << 11);
>  		I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
>  		I915_READ(fdi_rx_reg);

Do we need this in DPMS off part? As we only turn off enable bit?

>  
> @@ -1789,7 +1808,12 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
>  				}
>  			}
>  		}
> -
> +		temp = I915_READ(transconf_reg);
> +		/* BPC in transcoder is consistent with that in pipeconf */
> +		temp &= ~PIPE_BPC_MASK;
> +		temp |= pipe_bpc;
> +		I915_WRITE(transconf_reg, temp);
> +		I915_READ(transconf_reg);
>  		udelay(100);

Do we need this too after transcoder has been disabled?

>  
>  		/* disable PCH DPLL */
> -- 

-- 
Open Source Technology Center, Intel ltd.

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 198 bytes
Desc: Digital signature
URL: <http://lists.freedesktop.org/archives/intel-gfx/attachments/20100105/24fa1980/attachment.sig>