[Intel-gfx] [PATCH 01/11] drm/i915: flush CPU wc cache when flushing GTT write domain

[Daniel Vetter]

There are no other instructions that force the CPU to flush the wc
buffer before we tear down the corresponding fence reg with a
pipelined write. IIRC this _might_ get reordered, so enforce correct
ordering with a posting read to a harmless reg.

Also move one flush out from under an if (IS_I965), now that it
actually does something.

Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem.c |    7 ++++++-
 1 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d55541c..43b3b78 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2558,12 +2558,12 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
 		int ret;
 
 		i915_gem_object_flush_gpu_write_domain(obj);
-		i915_gem_object_flush_gtt_write_domain(obj);
 		ret = i915_gem_object_wait_rendering(obj);
 		if (ret != 0)
 			return ret;
 	}
 
+	i915_gem_object_flush_gtt_write_domain(obj);
 	i915_gem_clear_fence_reg (obj);
 
 	return 0;
@@ -2733,6 +2733,7 @@ i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
 static void
 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
 {
+	drm_i915_private_t *dev_priv = obj->dev->dev_private;
 	uint32_t old_write_domain;
 
 	if (obj->write_domain != I915_GEM_DOMAIN_GTT)
@@ -2741,7 +2742,11 @@ i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
 	/* No actual flushing is required for the GTT write domain.   Writes
 	 * to it immediately go to main memory as far as we know, so there's
 	 * no chipset flush.  It also doesn't land in render cache.
+	 * But flush the wc cache on the CPU.  For otherwise the fence teardown
+	 * for tiled buffers is not synchronized with any outstanding writes.
 	 */
+	I915_READ(IMR);
+
 	old_write_domain = obj->write_domain;
 	obj->write_domain = 0;
 
-- 
1.6.6