[Intel-gfx] [PATCH 05/11] drm/i915: flush CPU wc cache also in execbuf path

[Daniel Vetter]

In the execbuf path we batch up all global flushing operations.
I've forgotten to put the new CPU wc cache flushing there, so
fix this up.

Because we change relocations via wc-mapped gart, this _might_
actually fix some of the mysterious gpu hangs (due to corrupted
batchbuffers). Furthermore we would never observe these corruptions
from the cpu, because any reads to the device flush the wc cache
(and therefore fix up any inconsistencies).

Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 799b023..39781da 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1910,6 +1910,9 @@ i915_gem_flush(struct drm_device *dev,
 	if (flush_domains & I915_GEM_DOMAIN_CPU)
 		drm_agp_chipset_flush(dev);
 
+	if (flush_domains & I915_GEM_DOMAIN_GTT)
+		I915_READ(IMR);
+
 	if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
 		/*
 		 * read/write caches:
-- 
1.6.6