[Intel-gfx] [PATCH] drm/i915: Update write_domains on active list after flush.

[Chris Wilson]

On Sun, 31 Jan 2010 17:15:05 +0100, Daniel Vetter <daniel at ffwll.ch> wrote:
> Hi Chris,
> 
> You've beaten me by a few hours - I've just noticed your email while I was
> prepping my own forward port. One issue I've noticed while forward-proting
> your patch, see the inlined comment.

Ok, will need to readdress my comments on your error checking patch. We
currently can not have multiple write domains (as there really is only the
RENDER target that is gpu writable), all we need to ensure is that we can
actually read after a write (presuming that userspace manually flushes).
In this case, the kernel domain management is just conservative as it
cannot not about the midstream flush and so must presume that it never
occurs and so flush accordingly.

Daniel, can you respin your earlier patches as I think there were a couple
of good bug fixes that were lost in the noise. And then we can take a
fresh look at the others, and see if I said anything very silly.  :-)
-ickle

-- 
Chris Wilson, Intel Open Source Technology Centre