[Intel-gfx] [PATCH] drm/i915: don't access FW_BLC_SELF on 965G

Eric Anholt eric at anholt.net
Fri Jul 2 00:30:22 CEST 2010

On Wed, 30 Jun 2010 13:49:37 -0700, Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> The register offset for FW_BLC_SELF is a totally different set of bits
> on Broadwater (it's actually MI_RDRET_STATE), so don't treat it like
> FW_BLC_SELF on 965G chips.
> Fixes bug https://bugs.freedesktop.org/show_bug.cgi?id=26874.
> Cc: stable at kernel.org
> Tested-by: Norman Yarvin <yarvin at yarchive.net>
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>

Applied to for-linus.  Thanks!
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