[Intel-gfx] [PATCH] drm/i915: Make G4X-style PLL search more permissive

[Eric Anholt]

On Fri,  2 Jul 2010 16:43:30 -0400, Adam Jackson <ajax at redhat.com> wrote:
> Fixes an Ironlake laptop with a 68.940MHz 1280x800 panel and 120MHz SSC
> reference clock.
> 
> More generally, the 0.488% tolerance used before is just too tight to
> reliably find a PLL setting.  I extracted the search algorithm and
> modified it to find the dot clocks with maximum error over the valid
> range for the given output type:
> 
> http://people.freedesktop.org/~ajax/intel_g4x_find_best_pll.c
> 
> This gave:
> 
> Worst dotclock for Ironlake DAC refclk is 350000kHz (error 0.00571)
> Worst dotclock for Ironlake SL-LVDS refclk is 102321kHz (error 0.00524)
> Worst dotclock for Ironlake DL-LVDS refclk is 219642kHz (error 0.00488)
> Worst dotclock for Ironlake SL-LVDS SSC refclk is 84374kHz (error 0.00529)
> Worst dotclock for Ironlake DL-LVDS SSC refclk is 183035kHz (error 0.00488)
> Worst dotclock for G4X SDVO refclk is 50000kHz (error 0.17332)
> Worst dotclock for G4X HDMI refclk is 334400kHz (error 0.00478)
> Worst dotclock for G4X SL-LVDS refclk is 95571kHz (error 0.00449)
> Worst dotclock for G4X DL-LVDS refclk is 224000kHz (error 0.00510)

Applied to for-linus (with fixed commit msg for g4x sdvo).
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