[Intel-gfx] [PATCH] i915: fix ironlake edp panel setup (v2)

[Zhenyu Wang]

On 2010.06.29 09:47:04 -0400, Adam Jackson wrote:
> On Tue, 2010-06-29 at 16:44 +0800, Zhenyu Wang wrote:
> > On 2010.06.28 14:04:56 +0800, Zhenyu Wang wrote:
> > > 
> > > sorry, this is still broken on the 16x9 panel. 
> > > 
> > > 'intel_dp_link_required' is 107840*18/8 = 242640, 'intel_dp_max_data_rate' is
> > > 270000*1*8/10 = 216000. So it will fail in both check.
> > 
> > Dave, here's dmesg in working (upstream) and your patch applied cases.
> > Sorry, this panel does have EDID but is invalid.
> 
> That's not "has invalid EDID", that's "really doesn't have EDID at all".
> Might be DisplayID! 

yeah, no idea what it really is.

> Any chance you can try a patch like this and give
> me the dmesg?  It'll still look like an EDID failure but it should be
> something more interesting than cc cc cc cc ...

sure, will run this when I have access to the machine the next day.
the failure dmesg just showed the 1600x900 modeline is wrongly pruned.

> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index bd74b3f..16beed2 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -201,7 +201,7 @@ bool drm_edid_is_valid(struct edid *edid)
>  }
>  EXPORT_SYMBOL(drm_edid_is_valid);
>  
> -#define DDC_ADDR 0x50
> +#define DDC_ADDR 0x52
>  #define DDC_SEGMENT_ADDR 0x30
>  /**
>   * Get EDID information via I2C.
> 
> - ajax



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