[Intel-gfx] [PATCH 12/15] drm/i915: optimize fence-stealing for execbuf2

[Daniel Vetter]

Only wait for the gpu when the gpu is actually using this fence reg.
This should help with mixed execbuf2/old execbuf userspace in the
face of gtt access (cpu fallbacks).

v2: This was too buggy to describe in words. Fix it.

Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem.c |   24 +++++++++++++++---------
 1 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4bf8bf7..4102af6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2643,8 +2643,8 @@ int
 i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
 			      int pipelined)
 {
-	struct drm_device *dev = obj->dev;
 	struct drm_i915_gem_object *obj_priv = obj->driver_private;
+	int ret;
 
 	if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
 		return 0;
@@ -2655,18 +2655,24 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
 	 */
 	i915_gem_release_mmap(obj);
 
-	/* On the i915, GPU access to tiled buffers is via a fence,
-	 * therefore we must wait for any outstanding access to complete
-	 * before clearing the fence.
-	 */
-	if (!IS_I965G(dev)) {
-		int ret;
-
-		ret = i915_gem_object_flush_gpu_write_domain(obj, pipelined);
+	if (obj_priv->fenced_gpu_access) {
+		ret = i915_gem_object_flush_gpu_write_domain(obj, 1);
 		if (ret != 0)
 			return ret;
 	}
 
+	if (!pipelined) {
+		struct drm_device *dev = obj->dev;
+		drm_i915_private_t *dev_priv = dev->dev_private;
+		struct drm_i915_fence_reg *reg =
+			&dev_priv->fence_regs[obj_priv->fence_reg];
+		if (reg->last_rendering_seqno != 0) {
+			ret = i915_wait_request(dev, reg->last_rendering_seqno);
+			if (ret != 0)
+				return ret;
+		}
+	}
+
 	i915_gem_object_flush_gtt_write_domain(obj);
 	i915_gem_clear_fence_reg(obj, pipelined);
 
-- 
1.6.6.1