[Intel-gfx] [PATCH 05/13] agp/intel: Use a non-reserved value for the cache field of the PTEs.

[Eric Anholt]

On Thu, 18 Mar 2010 16:49:41 +0800, Zhenyu Wang <zhenyuw at linux.intel.com> wrote:
> On 2010.03.18 04:58:08 +0000, Owain Ainsworth wrote:
> > On Thu, Feb 25, 2010 at 11:09:48AM -0800, Eric Anholt wrote:
> > > I don't know if this is what we'll want to be using long term, we'll see.
> > > 
> > > Signed-off-by: Eric Anholt <eric at anholt.net>
> > 
> > Late (this has long been commited), but this doesn't actually do
> > anything:
> > 
> > we declare cache_bits, set it to a value, then do *nothing* with it.
> > 
> > was this intended to be ORed into the writel?
> > 
> 
> yeah, that's the original idea, and I have a patch to rework the PTE cache
> bits setting for Sanbybridge, like using new agp_type_to_mask_type hook, etc.
> But as this hardware is still new, I haven't finalized the real proper cache
> setting in GTT PTE yet.

And the iommu path doesn't apparently try to get it set at all.

I'd love to see more of the AGP hook stuff die.  It's all so thoroughly
generalized with hooks everywhere now you can never see what's
happening, like whether your cache type bits are ending up in your page
table entries or not.  I'd much rather see the chipset insert_entries
functions just do the work they need to do, including bit shifting for
larger than 32bits and cache mode setting.
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