[Intel-gfx] [PATCH 5/7] drm/i915: use vblank and vsync interrupts on 945

[Jesse Barnes]

On 945, vblank delivery alone seems unreliable.  The PIPE*STAT bits get
set correctly, but interrupts occur at a low frequency relative to
refresh.  If we enable VSYNC interrupts as well however (even though we
only check for VBLANK interrupts when handling) we get the right
frequency.  Increases OA performance on my AspireOne by about 300% with
the new DRI2 bits, which rely on high frequency vblank events.

Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_irq.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9519346..b16bb0d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -45,8 +45,8 @@
  */
 #define I915_INTERRUPT_ENABLE_FIX			\
 	(I915_ASLE_INTERRUPT |				\
-	 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |		\
-	 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |		\
+	 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |		\
+	 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT |		\
 	 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |	\
 	 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |	\
 	 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
@@ -1132,6 +1132,7 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
 				     PIPE_START_VBLANK_INTERRUPT_ENABLE);
 	else
 		i915_enable_pipestat(dev_priv, pipe,
+				     PIPE_VSYNC_INTERRUPT_ENABLE |
 				     PIPE_VBLANK_INTERRUPT_ENABLE);
 	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 	return 0;
@@ -1151,6 +1152,7 @@ void i915_disable_vblank(struct drm_device *dev, int pipe)
 					     DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
 	else
 		i915_disable_pipestat(dev_priv, pipe,
+				      PIPE_VSYNC_INTERRUPT_ENABLE |
 				      PIPE_VBLANK_INTERRUPT_ENABLE |
 				      PIPE_START_VBLANK_INTERRUPT_ENABLE);
 	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
-- 
1.6.1.3