[Intel-gfx] Modesetting bug on 945GSE (Atom N270) with Chris Wilson drm-intel-next kernel

[Simon Farnsworth]

On Friday 19 November 2010, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> On Fri, 19 Nov 2010 17:44:49 +0000, Simon Farnsworth <simon.farnsworth at onelan.co.uk> wrote:
> > Hello,
> > 
> > I'm seeing an interesting bug on 945GSE, and I have absolutely no idea
> > where to start looking. I'm trying to deal with performance issues on
> > this platform, so I'm updating to master of as many bits as possible, to
> > see if they're better.
> 
> Do you use a lot of fences? If so the pipelined fencing may be of interest
> and also the relaxed fencing rules for i945. It would be good to get
> some feedback on those.
> 
I'm a dumb applications programmer :)

I'm seeing an OpenGL compositor (using TFP to get window contents for circa 10
windows) struggle to meet frame deadlines at 60Hz. I would therefore guess
that I do use quite a few fences, as if I've understood properly, each of the
various window contents is accessed via a fence.

> > drm-intel-next as of a17577c9 (not tried older versions yet) is
> > consistently rendering to the middle third or so of the screen only;
> > this is happening in X, as well as in inteldrmfb during boot.
> 
> Vertical or horizontal offset? Which outputs? Anything suspicious in
> intel_reg_dumper?
> -Chris
It's horizontal that's broken. I'm using VGA (but can test DVI if you think
it's output-specific). I didn't spot anything weird in intel_reg_dumper, but
there are changes:

--- regs.good   2010-11-22 09:43:22.909797682 +0000
+++ regs.bad    2010-11-22 09:59:12.088372307 +0000
@@ -22,7 +22,7 @@
        DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
       RENCLK_GATE_D1: 0x00000000
       RENCLK_GATE_D2: 0x00000000
-               SDVOB: 0x80480084 (enabled, pipe A, stall disabled, detected)
+               SDVOB: 0x80480004 (enabled, pipe A, stall disabled, detected)
                SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected)
              SDVOUDI: 0x00000020
               DSPARB: 0x00001d9c
@@ -32,21 +32,21 @@
                 ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
                 LVDS: 0x40000000 (disabled, pipe B, 18 bit, 1 channel)
                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
-                DVOB: 0x80480084 (enabled, pipe A, no stall, -hsync, -vsync)
+                DVOB: 0x80480004 (enabled, pipe A, no stall, -hsync, -vsync)
                 DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
          DVOA_SRCDIM: 0x00000000
          DVOB_SRCDIM: 0x00000000
          DVOC_SRCDIM: 0x00000000
           PP_CONTROL: 0x00000000 (power target: off)
            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
-        PP_ON_DELAYS: 0x00000000
-       PP_OFF_DELAYS: 0x00000000
+        PP_ON_DELAYS: 0x019007d0
+       PP_OFF_DELAYS: 0x015e07d0
           PP_DIVISOR: 0x00270f04
         PFIT_CONTROL: 0x00000000
      PFIT_PGM_RATIOS: 0x00000000
      PORT_HOTPLUG_EN: 0x04000220
    PORT_HOTPLUG_STAT: 0x00000400
-            DSPACNTR: 0x41000000 (disabled, pipe B)
+            DSPACNTR: 0xc1000000 (enabled, pipe B)
           DSPASTRIDE: 0x00000c80 (3200 bytes)
              DSPAPOS: 0x00000000 (0, 0)
             DSPASIZE: 0x03ff04ff (1280, 1024)
@@ -79,10 +79,10 @@
           DSPBSTRIDE: 0x00002000 (8192 bytes)
              DSPBPOS: 0x00000000 (0, 0)
             DSPBSIZE: 0x0419068f (1680, 1050)
-            DSPBBASE: 0x07000000
+            DSPBBASE: 0x02000000
             DSPBSURF: 0x00000000
          DSPBTILEOFF: 0x00000000
-           PIPEBCONF: 0x00000000 (disabled, single-wide)
+           PIPEBCONF: 0x80000000 (enabled, single-wide)

-- 
Simon Farnsworth
Software Engineer
ONELAN Limited
http://www.onelan.com/