[Intel-gfx] [PATCH] CHROMIUM: i915: Initialize panel timing registers if VBIOS did not.

[Bryan Freed]

The time between start of the pixel clock and backlight enable is a basic
panel timing constraint.  If no VBIOS Table is found, and the Panel Power
On/Off registers are found to be 0, assume we are booting without VBIOS
initialization and set these registers to something reasonable.

TEST=Repeat the 'xset dpms force {off|on}' sequence.

Change-Id: Ibed6cc10d46bf52fd92e0beb25ae3525b5eef99d
Signed-off-by: Bryan Freed <bfreed at chromium.org>
---
 drivers/gpu/drm/i915/intel_bios.c |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index ad030ff..83d7371 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -508,6 +508,26 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
 }

 /**
+ * init_regs_no_vbt - Directly write registers that are usually set by
VBIOS.
+ *
+ * This goes beyond the registers that this driver controls with settings
found
+ * in the VBIOS Table.  If there is no VBIOS table, and certain registers
are
+ * uninitialized, set them here.
+ */
+static void
+init_regs_no_vbt(struct drm_i915_private *dev_priv)
+{
+ /* Set the Panel Power On/Off timings if unitialized. */
+ if ((I915_READ(PP_ON_DELAYS) == 0) && (I915_READ(PP_OFF_DELAYS) == 0)) {
+ /* Set T2 to 40ms and T5 to 200ms */
+ I915_WRITE(PP_ON_DELAYS, 0x019007d0);
+
+ /* Set T3 to 35ms and Tx to 200ms */
+ I915_WRITE(PP_OFF_DELAYS, 0x015e07d0);
+ }
+}
+
+/**
  * intel_init_bios - initialize VBIOS settings & find VBT
  * @dev: DRM device
  *
@@ -550,6 +570,7 @@ intel_init_bios(struct drm_device *dev)
  if (!vbt) {
  DRM_ERROR("VBT signature missing\n");
  pci_unmap_rom(pdev, bios);
+ init_regs_no_vbt(dev_priv);
  return -1;
  }

-- 
1.7.1
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