[Intel-gfx] [PATCH] enable blt acceleration on gen6

[Zou, Nanhai]

>>-----Original Message-----
>>From: intel-gfx-bounces+nanhai.zou=intel.com at lists.freedesktop.org
>>[mailto:intel-gfx-bounces+nanhai.zou=intel.com at lists.freedesktop.org] On
>>Behalf Of Zou, Nanhai
>>Sent: 2010年10月28日 9:02
>>To: Chris Wilson; intel-gfx at lists.freedesktop.org
>>Subject: Re: [Intel-gfx] [PATCH] enable blt acceleration on gen6
>>
>>
>>
>>>>-----Original Message-----
>>>>From: Chris Wilson [mailto:chris at chris-wilson.co.uk]
>>>>Sent: 2010年10月27日 17:08
>>>>To: Zou, Nanhai; intel-gfx at lists.freedesktop.org
>>>>Subject: Re: [Intel-gfx] [PATCH] enable blt acceleration on gen6
>>>>
>>>>On Wed, 27 Oct 2010 14:47:32 +0800, Zou Nan hai <nanhai.zou at intel.com> wrote:
>>>>> uxa: enable blt acceleration on gen6 hardware.
>>>>
>>>>That's pretty close to what I had in mind. I thought adding
>>>>intel_batch_set_mode(BLT), intel_batch_set_mode(RENDER) etc a bit more
>>>>explicit. That gives us a single point at which we can detect a context
>>>>switch and perform workarounds, rather than just continuing to add them ad
>>>>hoc.
>>>>
>>>>e.g.
>>>>static inline void
>>>>intel_batch_set_mode(struct intel_screen_private *intel, int mode)
>>>>{
>>>>  if (mode == intel->batch.mode)
>>>>    return;
>>>>
>>>>  intel->batch.context_switch(intel, mode);
>>>>  intel->batch.mode = mode;
>>>>}
>>>>
>>>>static void
>>>>gen6_batch_context_switch(struct intel_screen_private *intel,
>>>>                          int mode)
>>>>{
>>>>  intel_batch_flush(intel);
>>>>  intel->batch.ring = mode;
>>>>}
>>>>
>>>>static void
>>>>gen5_batch_context_switch(struct intel_screen_private *intel,
>>>>                          int mode)
>>>>{
>>>>  if (intel->batch.mode == BLT) {
>>>>	OUT_BATCH(3D_NP); /* 2D->3D non-pipeling workaround */
>>>>  }
>>>>  intel_batch_flush(intel);
>>>>}
>>>>
>>>>void intel_batch_submit(struct intel_screen_private *intel)
>>>>{
>>>>  execbuf.flags |= intel->batch.ring;
>>>>  ...
>>>>  intel->batch.mode = NONE;
>>>>}
>>>>
>>>>etc. [Forgive me the bit of poetic licence in those snippets.] The only
>>>>nasty side-effect of that is that you need to perform the
>>>>intel_batch_set_mode() in both the prepare and done routines (in case the
>>>>batch is emitted before done()).
>>>>
>>>>Btw, why the 32 NOOP workaround? I haven't stumbled across the reason
>>>>for that yet.
>>
>>I see in doc the 32 NOOP workaround but it does not tell the reason.
>>Without this some heavy workload like x11perf may hang.
>>
>>Zou Nan hai
>>>>
>>>>Your patch works as advertised with just a s/I915_EXEC_BLIT/I915_EXEC_BLT/.
>>>>-Chris
>>
>>Thanks
>>>>
I found we should set the walkaround in kernel
(every time ring tail is moved, the first command in ring is MI_BATCH_BUFFER_START)
So I have removed the walkaround code and resent the patch.
We will sent another patch to add the walkaround in kernel.

Thanks
Zou nan hai

>>>>--
>>>>Chris Wilson, Intel Open Source Technology Centre
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