[Intel-gfx] [intel-gfx][PATCH 2/2] drm/i915: Add a new ring buffer on Sandybridge

[Zhenyu Wang]

On 2010.09.03 09:57:37 +0800, Xiang, Haihao wrote:
> > 
> > If I'm not completely mistaken, all these ringbuffer register have the
> > same offsets over a common base: 0x02000 for the render ring, 0x04000 for
> > bsd on gen5, 0x12000 for bsd on gen6.
> Some registers (e.g. HSW_PGA) don't follow this rule.

which you can explicitly note it in ring struct.

> Even if the register follows the above rule, we can not expect to use
> the same function to access this register. E.g. Setting TAIL for this
> new ring buffer must follow a special sequence on Sandybridge.
> 

you only need to handle it specially in ring advance function. I'd like
to only leave ring specific functions as

- ring cache flush
- ring new request
- ring seqno state
- ring irq handling

others are so common for all rings.

-- 
Open Source Technology Center, Intel ltd.

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