[Intel-gfx] [PATCH 06/21] drm/i915: Pass the fence register number to be written
Chris Wilson
chris at chris-wilson.co.uk
Sat Apr 16 11:17:30 CEST 2011
This simplifies a later change where we want to successfully write (or
pipeline) the fence update prior to updating the bo.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch>
---
drivers/gpu/drm/i915/i915_gem.c | 61 ++++++++++++++++++--------------------
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 30 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0ccd3ab..8c835de 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2349,12 +2349,12 @@ i915_gpu_idle(struct drm_device *dev)
}
static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
- struct intel_ring_buffer *pipelined)
+ struct intel_ring_buffer *pipelined,
+ int reg)
{
struct drm_device *dev = obj->base.dev;
drm_i915_private_t *dev_priv = dev->dev_private;
u32 size = obj->gtt_space->size;
- int regnum = obj->fence_reg;
uint64_t val;
val = (uint64_t)((obj->gtt_offset + size - 4096) &
@@ -2374,24 +2374,24 @@ static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
intel_ring_emit(pipelined, MI_NOOP);
intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
- intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
+ intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + reg*8);
intel_ring_emit(pipelined, (u32)val);
- intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
+ intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + reg*8 + 4);
intel_ring_emit(pipelined, (u32)(val >> 32));
intel_ring_advance(pipelined);
} else
- I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
+ I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
return 0;
}
static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
- struct intel_ring_buffer *pipelined)
+ struct intel_ring_buffer *pipelined,
+ int reg)
{
struct drm_device *dev = obj->base.dev;
drm_i915_private_t *dev_priv = dev->dev_private;
u32 size = obj->gtt_space->size;
- int regnum = obj->fence_reg;
uint64_t val;
val = (uint64_t)((obj->gtt_offset + size - 4096) &
@@ -2409,25 +2409,25 @@ static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
intel_ring_emit(pipelined, MI_NOOP);
intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
- intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
+ intel_ring_emit(pipelined, FENCE_REG_965_0 + reg*8);
intel_ring_emit(pipelined, (u32)val);
- intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
+ intel_ring_emit(pipelined, FENCE_REG_965_0 + reg*8 + 4);
intel_ring_emit(pipelined, (u32)(val >> 32));
intel_ring_advance(pipelined);
} else
- I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
+ I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
return 0;
}
static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
- struct intel_ring_buffer *pipelined)
+ struct intel_ring_buffer *pipelined,
+ int reg)
{
struct drm_device *dev = obj->base.dev;
drm_i915_private_t *dev_priv = dev->dev_private;
u32 size = obj->gtt_space->size;
- u32 fence_reg, val, pitch_val;
- int tile_width;
+ int tile_width, val;
if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
(size & -size) != size ||
@@ -2441,22 +2441,17 @@ static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
else
tile_width = 512;
- /* Note: pitch better be a power of two tile widths */
- pitch_val = obj->stride / tile_width;
- pitch_val = ffs(pitch_val) - 1;
-
val = obj->gtt_offset;
if (obj->tiling_mode == I915_TILING_Y)
val |= 1 << I830_FENCE_TILING_Y_SHIFT;
val |= I915_FENCE_SIZE_BITS(size);
- val |= pitch_val << I830_FENCE_PITCH_SHIFT;
+ val |= I915_FENCE_PITCH_BITS(obj->stride / tile_width);
val |= I830_FENCE_REG_VALID;
- fence_reg = obj->fence_reg;
- if (fence_reg < 8)
- fence_reg = FENCE_REG_830_0 + fence_reg * 4;
+ if (reg < 8)
+ reg = FENCE_REG_830_0 + reg * 4;
else
- fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
+ reg = FENCE_REG_945_8 + (reg - 8) * 4;
if (pipelined) {
int ret = intel_ring_begin(pipelined, 4);
@@ -2465,22 +2460,22 @@ static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
intel_ring_emit(pipelined, MI_NOOP);
intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit(pipelined, fence_reg);
+ intel_ring_emit(pipelined, reg);
intel_ring_emit(pipelined, val);
intel_ring_advance(pipelined);
} else
- I915_WRITE(fence_reg, val);
+ I915_WRITE(reg, val);
return 0;
}
static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
- struct intel_ring_buffer *pipelined)
+ struct intel_ring_buffer *pipelined,
+ int reg)
{
struct drm_device *dev = obj->base.dev;
drm_i915_private_t *dev_priv = dev->dev_private;
u32 size = obj->gtt_space->size;
- int regnum = obj->fence_reg;
uint32_t val;
uint32_t pitch_val;
@@ -2508,11 +2503,11 @@ static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
intel_ring_emit(pipelined, MI_NOOP);
intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
+ intel_ring_emit(pipelined, FENCE_REG_830_0 + reg*4);
intel_ring_emit(pipelined, val);
intel_ring_advance(pipelined);
} else
- I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
+ I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
return 0;
}
@@ -2653,6 +2648,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
struct drm_device *dev = obj->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_i915_fence_reg *reg;
+ int regnum;
int ret;
/* XXX disable pipelining. There are bugs. Shocking. */
@@ -2748,19 +2744,20 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
update:
obj->tiling_changed = false;
+ regnum = reg - dev_priv->fence_regs;
switch (INTEL_INFO(dev)->gen) {
case 6:
- ret = sandybridge_write_fence_reg(obj, pipelined);
+ ret = sandybridge_write_fence_reg(obj, pipelined, regnum);
break;
case 5:
case 4:
- ret = i965_write_fence_reg(obj, pipelined);
+ ret = i965_write_fence_reg(obj, pipelined, regnum);
break;
case 3:
- ret = i915_write_fence_reg(obj, pipelined);
+ ret = i915_write_fence_reg(obj, pipelined, regnum);
break;
case 2:
- ret = i830_write_fence_reg(obj, pipelined);
+ ret = i830_write_fence_reg(obj, pipelined, regnum);
break;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e6bfe94..8848411 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -264,6 +264,7 @@
#define I915_FENCE_START_MASK 0x0ff00000
#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
+#define I915_FENCE_PITCH_BITS(stride) ((ffs(stride) - 1) << I830_FENCE_PITCH_SHIFT)
#define FENCE_REG_965_0 0x03000
#define I965_FENCE_PITCH_SHIFT 2
--
1.7.4.1
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