[Intel-gfx] [PATCH 4/5] drm/i915: fix relaxed tiling on gen2: y-tiling on i855gm

[Daniel Vetter]

Experiments showed that y-tiled access from the cpu doesn't work on my gen2
machine.

Checking this in create_mmap_offset does not work due to libdrm bo reuse.

Chris Wilson also clarified (by checking internal docs) that only i855GM has
broken y-tiled fences for cpu access (guess what hw I own). Hence move the check
to deny y-tiled access to gem_fault and restrict it with IS_I85X. According to
docs, upload _should_ work to y-tiled textures with the blitter on all gen2
chips.

Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f658f4f..6471d51 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1255,6 +1255,13 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 		goto unlock;
 	}
 
+	/* i855gm has broken y-tiled fences for cpu access, blitter should work,
+	 * though. */
+	if (IS_I85X(dev) && obj->tiling_mode == I915_TILING_Y) {
+		ret = -EINVAL;
+		goto unlock;
+	}
+
 	/* Now bind it into the GTT if needed */
 	if (!obj->map_and_fenceable) {
 		ret = i915_gem_object_unbind(obj);
-- 
1.7.4.1