[Intel-gfx] [RFC] drm/i915: use PIPE_CONTROL for flushing on gen6+

[Jesse Barnes]

On Fri, 12 Aug 2011 16:55:47 -0700
Eric Anholt <eric at anholt.net> wrote:

> On Fri, 12 Aug 2011 11:18:45 -0700, Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> > I'm trying to figure out why this doesn't work.  Anyone have ideas?
> > 
> > On gen6+ (well probably since Cantiga actually) we're supposed to use
> > PIPE_CONTROL rather than MI_FLUSH for flushing the pipeline and
> > caches.  This patch doesn't cause hangs or crashes in my testing, but
> > does prevent glxgears from displaying anything.
> > 
> > The other worrying thing about this is that gen6+ has a command length
> > field of 3, but we're using 2 in the DRI driver, even on gen6.
> > Changing it doesn't seem to have any effect, but it's still of concern.
> 
> From what I've read, the hardware tends to process shortened packets
> using some garbage in whatever fields were left out.
> 
> I don't see why we'd need a separate object for the pipe control write
> destination.  We could just drop it in some unused bit of the status
> page, right?

Yeah, that would be fine.  I just re-used the scratch page from ILK
since we already had code for it, but on SNB it should be safe to just
use the HWS.

> I'd drop the scratch_addr from packets that don't do a post-sync write,
> for clarity.
> 
> I don't see what's actually going wrong in this patch, though.

I tried adding the TLB flush, which was missing, but I still see big
missing regions on the login screen.  I guess even blits somehow aren't
landing or getting sequenced correctly... back to the docs to look for
more clues.

-- 
Jesse Barnes, Intel Open Source Technology Center