[Intel-gfx] [PATCH 2/3] drm/i915: Force sync command ordering (Gen6+)

[Jesse Barnes]

On Wed, 07 Dec 2011 12:54:07 -0800
Eric Anholt <eric at anholt.net> wrote:

> On Wed, 7 Dec 2011 11:58:05 -0800, Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> > On Wed, 7 Dec 2011 10:38:41 -0800
> > Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> > 
> > > On Wed, 07 Dec 2011 10:35:45 -0800
> > > Eric Anholt <eric at anholt.net> wrote:
> > > 
> > > > On Sat, 22 Oct 2011 19:41:24 -0700, Ben Widawsky <ben at bwidawsk.net> wrote:
> > > > > The docs say this is required for Gen7, and since the bit was added for
> > > > > Gen6, we are also setting it there pit pf paranoia. Particularly as
> > > > > Chris points out, if PIPE_CONTROL counts as a 3d state packet.
> > > > > 
> > > > > This was found through doc inspection by Ken and applies to Gen6+;
> > > > > 
> > > > > Cc: Keith Packard <keithp at keithp.com>
> > > > > Reported-by: Kenneth Graunke <kenneth at whitecape.org>
> > > > > Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> > > > > Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
> > > > > Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> > > > 
> > > > Reviewed-by: Eric Anholt <eric at anholt.net>
> > > > 
> > > > however, it doesn't appear to help Ivybridge IRQ troubles.
> > > 
> > > You could try something like the below to force the use of PIPE_NOTIFY
> > > instead.  Only lightly tested on IVB when we had lots of other bugs, so
> > > I'm not sure if it works at all.
> > 
> > Though if it's the blit ring hanging, you'd have to try using a
> > flush_dw notify (if such a thing exists) instead...
> 
> Yeah, MI_FLUSH_DW as opposed to MI_STORE_DW + MI_USER_INTERRUPT.

Looks like there is a notify option, bit 8 of MI_FLUSH_DW.  It's a long
shot, but does anyone want to give it a try?

-- 
Jesse Barnes, Intel Open Source Technology Center
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