[Intel-gfx] [PATCH 09/43] drm/i915: introduce a vtable for gpu core functions

Daniel Vetter daniel.vetter at ffwll.ch
Wed Dec 14 13:57:06 CET 2011


... like for forcewake, which protects everything _but_ display.
Expect more things (like gtt abstractions, rings, inter-ring sync)
to come.

Signed-Off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c      |    6 +++---
 drivers/gpu/drm/i915/i915_drv.h      |    8 ++++++--
 drivers/gpu/drm/i915/intel_display.c |    8 ++++----
 3 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 653b6f2..4a2eb68 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -372,7 +372,7 @@ void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 
 	spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 	if (dev_priv->forcewake_count++ == 0)
-		dev_priv->display.force_wake_get(dev_priv);
+		dev_priv->core.force_wake_get(dev_priv);
 	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 }
 
@@ -397,7 +397,7 @@ void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 
 	spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 	if (--dev_priv->forcewake_count == 0)
-		dev_priv->display.force_wake_put(dev_priv);
+		dev_priv->core.force_wake_put(dev_priv);
 	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 }
 
@@ -650,7 +650,7 @@ int i915_reset(struct drm_device *dev, u8 flags)
 		/* If reset with a user forcewake, try to restore */
 		spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 		if (dev_priv->forcewake_count)
-			dev_priv->display.force_wake_get(dev_priv);
+			dev_priv->core.force_wake_get(dev_priv);
 		spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 		break;
 	case 5:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4ee4626..40e0848 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -215,8 +215,6 @@ struct drm_i915_display_funcs {
 			  struct drm_i915_gem_object *obj);
 	int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 			    int x, int y);
-	void (*force_wake_get)(struct drm_i915_private *dev_priv);
-	void (*force_wake_put)(struct drm_i915_private *dev_priv);
 	/* clock updates for mode set */
 	/* cursor updates */
 	/* render clock increase/decrease */
@@ -224,6 +222,11 @@ struct drm_i915_display_funcs {
 	/* pll clock increase/decrease */
 };
 
+struct drm_i915_core_funcs {
+	void (*force_wake_get)(struct drm_i915_private *dev_priv);
+	void (*force_wake_put)(struct drm_i915_private *dev_priv);
+};
+
 struct intel_device_info {
 	u8 gen;
 	u8 is_mobile:1;
@@ -296,6 +299,7 @@ typedef struct drm_i915_private {
 	struct pci_dev *bridge_dev;
 	struct intel_ring_buffer ring[I915_NUM_RINGS];
 	uint32_t next_seqno;
+	struct drm_i915_core_funcs core;
 
 	drm_dma_handle_t *status_page_dmah;
 	uint32_t counter;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 70436c7..2f0cc52 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8491,8 +8491,8 @@ static void intel_init_display(struct drm_device *dev)
 
 	/* For FIFO watermark updates */
 	if (HAS_PCH_SPLIT(dev)) {
-		dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
-		dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
+		dev_priv->core.force_wake_get = __gen6_gt_force_wake_get;
+		dev_priv->core.force_wake_put = __gen6_gt_force_wake_put;
 
 		/* IVB configs may use multi-threaded forcewake */
 		if (IS_IVYBRIDGE(dev)) {
@@ -8506,9 +8506,9 @@ static void intel_init_display(struct drm_device *dev)
 
 			if (ecobus & FORCEWAKE_MT_ENABLE) {
 				DRM_DEBUG_KMS("Using MT version of forcewake\n");
-				dev_priv->display.force_wake_get =
+				dev_priv->core.force_wake_get =
 					__gen6_gt_force_wake_mt_get;
-				dev_priv->display.force_wake_put =
+				dev_priv->core.force_wake_put =
 					__gen6_gt_force_wake_mt_put;
 			}
 		}
-- 
1.7.7.3




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