[Intel-gfx] [PATCH] drm/i915: Modify for pineview clock source

[bfreed at chromium.org]

From: Bryan Freed <bfreed at google.com>

The i915 driver normally assumes the video bios has configured several
of the LVDS panel registers, and it just inherits the values. If the
vbios has not run, several of these will need to be setup.

intel_bios.c: default clock source selection on pineview to use the SSC source.

If these are not correct then although the panel looks ok, output from an HDMI
encoder (eg, Chrontel CH7036) will be incorrect.

Signed-off-by: Mark Hayter <mdhayter at chromium.org>
---
 drivers/gpu/drm/i915/intel_bios.c |   17 ++++++++++++++++-
 1 files changed, 16 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index b0b1200..a1c7269 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -555,9 +555,20 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
 	return;
 }
 
+static int intel_bios_ssc_frequency(struct drm_device *dev, bool high_speed)
+{
+	if (IS_GEN2(dev))
+		return high_speed ? 66 : 48;
+	if (IS_GEN3(dev) || IS_GEN4(dev))
+		return high_speed ? 100 : 96;
+	return high_speed ? 120 : 100;
+}
+
 static void
 init_vbt_defaults(struct drm_i915_private *dev_priv)
 {
+	struct drm_device *dev = dev_priv->dev;
+
 	dev_priv->crt_ddc_pin = GMBUS_PORT_VGADDC;
 
 	/* LFP panel data */
@@ -570,7 +581,11 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
 	/* general features */
 	dev_priv->int_tv_support = 1;
 	dev_priv->int_crt_support = 1;
-	dev_priv->lvds_use_ssc = 0;
+
+	/* Default to using SSC */
+	dev_priv->lvds_use_ssc = 1;
+	dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);
+	DRM_DEBUG("Set default to SSC at %dMHz\n", dev_priv->lvds_ssc_freq);
 
 	/* eDP data */
 	dev_priv->edp.bpp = 18;
-- 
1.7.3.1