[Intel-gfx] [PATCH] drm/i915: set cache sharing policy to max sharing on SNB+

[Chris Wilson]

On Fri,  1 Jul 2011 16:35:07 -0700, Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> By default, the GPU will only share a very small portion of the CPU
> cache.  With this change, both the GPU and CPU will have full access to
> the cache, which should help (sometimes a lot) in most cases.

Joy, this looks to be at best a mixed blessing. For CPU bound games like
padman, it degrades performance by about 5% on my desktop SNB. But for
nexuiz, there appears to be little change. The ddx shows further regression
of the order of 10%. The immediate suspect is that it hurts the use of
pixman for trapezoid mask generation, which whilst being less than ideal
behaviour and will be fixed in the near future, is indicative of the sort
of negative impact this change will have on CPU-memory bound applications.
Conversely the equivalent spans-based code is about the only example I
found that is sped up by the patch, by about 3%.

Having just checked up on 0x900c, I'm even more confused. From my old
specs, the register is SNPCR, the snoop control register, which makes
more sense than MBC, and that 0<<21 is for the maximum uncore resources,
the default setting and the default on my SNB, with 1<<21 being the
medium setting. Now, the only reference I have is the register dump with
no explanation of what the resource that is actually being controlled...
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre