[Intel-gfx] [PATCH] drm/i915: set persistent mode for fbc

[Ben Widawsky]

On Sun, Jul 03, 2011 at 12:01:47PM +0100, Chris Wilson wrote:
> I think we can make the patch and resulting code a bit more
> comprehensible...
> 
> On Fri,  1 Jul 2011 12:48:43 -0700, Ben Widawsky <ben at bwidawsk.net> wrote:
> > This seems to fix my bugs with sna enabled.
> > 
> > We should collect some power numbers, and validate it works on ILK
> > before upstreaming. (And read more about what it actually does).
> > 
> > Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c |    2 ++
> >  1 files changed, 2 insertions(+), 0 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 804ac4d..4b94d71 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1607,6 +1607,8 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
> >  		I915_WRITE(SNB_DPFC_CTL_SA,
> >  			   SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
> >  		I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
> > +		/* Set persistent mode */
> > +		I915_WRITE(ILK_DPFC_CONTROL, 1 << 25);
> /* Set persistent mode for front-buffer rendering and to detect direct
>  * writes through the CPU */
> I915_WRITE(ILK_DPFC_CONTROL,
>            I915_READ(ILK_DPFC_CONTROL) | DPFC_CTL_PERSISTENT_MODE);
> -Chris

Looks good to me. I'd like to get some power numbers from Jesse though
before going for -fixes.

Would you care to resend your patch with your description from the
earlier mail as the commit message?

Ben