[Intel-gfx] [PATCH 3/6] drm/i915: Set persistent-mode for ILK/SNB framebuffer compression

[Jesse Barnes]

On Thu,  7 Jul 2011 12:48:08 +0100
Chris Wilson <chris at chris-wilson.co.uk> wrote:

> Persistent mode is intended for use with front-buffer rendering, such as
> X, where it is necessary to detect writes to the scanout either by the
> GPU or through the CPU's fence, and recompress the dirty regions on the
> fly. (By comparison to the back-buffer rendering, the scanout is always
> recompressed after a page-flip.)
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=33487
> References: https://bugs.freedesktop.org/show_bug.cgi?id=31742
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    1 +
>  drivers/gpu/drm/i915/intel_display.c |    2 ++
>  2 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5d5def7..86a75bc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -579,6 +579,7 @@
>  #define   DPFC_CTL_PLANEA	(0<<30)
>  #define   DPFC_CTL_PLANEB	(1<<30)
>  #define   DPFC_CTL_FENCE_EN	(1<<29)
> +#define   DPFC_CTL_PERSISTENT_MODE	(1<<25)
>  #define   DPFC_SR_EN		(1<<10)
>  #define   DPFC_CTL_LIMIT_1X	(0<<6)
>  #define   DPFC_CTL_LIMIT_2X	(1<<6)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0cbae6c..8ff0eae 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1579,6 +1579,8 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
>  
>  	dpfc_ctl &= DPFC_RESERVED;
>  	dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
> +	/* Set persistent mode for front-buffer rendering, ala X. */
> +	dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
>  	dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
>  	I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
>  

Yes, extra bits!  Looks like the latest specs don't restrict this bit
to being SNB only or anything, so setting it here looks good.

Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center