[Intel-gfx] [PATCH 06/10] Xv: Refactor out pipeline setup functions for future reuse in render.
Kenneth Graunke
kenneth at whitecape.org
Thu Jul 14 23:21:19 CEST 2011
While we're at it, make the functions simply take an intel_screen_private
pointer directly instead of having to fetch it from ScrnInfoPtr.
Also coalesce some gen6/gen7 functions that were 98% identical.
Cc: Xiang, Haihao <haihao.xiang at intel.com>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
src/Makefile.am | 1 +
src/i965_3d.c | 430 ++++++++++++++++++++++++++++++++++++++++++++++
src/i965_video.c | 500 +++---------------------------------------------------
src/intel.h | 29 +++
4 files changed, 482 insertions(+), 478 deletions(-)
create mode 100644 src/i965_3d.c
diff --git a/src/Makefile.am b/src/Makefile.am
index a7f219c..cd1bb36 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -67,6 +67,7 @@ intel_drv_la_SOURCES = \
i915_render.c \
i915_video.c \
i965_reg.h \
+ i965_3d.c \
i965_video.c \
i965_render.c \
$(NULL)
diff --git a/src/i965_3d.c b/src/i965_3d.c
new file mode 100644
index 0000000..19ddee7
--- /dev/null
+++ b/src/i965_3d.c
@@ -0,0 +1,430 @@
+/*
+ * Copyright © 2011 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <string.h>
+
+#include "intel.h"
+#include "i965_reg.h"
+#include "brw_defines.h"
+#include "brw_structs.h"
+
+void
+gen6_upload_invariant_states(intel_screen_private *intel)
+{
+ Bool ivb = INTEL_INFO(intel)->gen >= 70;
+
+ OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
+ OUT_BATCH(BRW_PIPE_CONTROL_IS_FLUSH |
+ BRW_PIPE_CONTROL_WC_FLUSH |
+ BRW_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ BRW_PIPE_CONTROL_NOWRITE);
+ OUT_BATCH(0); /* write address */
+ OUT_BATCH(0); /* write data */
+
+ OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+
+ OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | ((ivb ? 4 : 3) - 2));
+ OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
+ GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
+ OUT_BATCH(0);
+ if (ivb)
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
+ OUT_BATCH(1);
+
+ /* Set system instruction pointer */
+ OUT_BATCH(BRW_STATE_SIP | 0);
+ OUT_BATCH(0);
+}
+
+void
+gen6_upload_viewport_state_pointers(intel_screen_private *intel,
+ drm_intel_bo *cc_vp_bo)
+{
+ OUT_BATCH(GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
+ GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
+ (4 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_RELOC(cc_vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+}
+
+void
+gen7_upload_viewport_state_pointers(intel_screen_private *intel,
+ drm_intel_bo *cc_vp_bo)
+{
+ OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
+ OUT_RELOC(cc_vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+
+ OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
+ OUT_BATCH(0);
+}
+
+void
+gen6_upload_urb(intel_screen_private *intel)
+{
+ OUT_BATCH(GEN6_3DSTATE_URB | (3 - 2));
+ OUT_BATCH(((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) |
+ (24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
+ OUT_BATCH((0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) |
+ (0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */
+}
+
+/*
+ * URB layout on GEN7
+ * ----------------------------------------
+ * | PS Push Constants (8KB) | VS entries |
+ * ----------------------------------------
+ */
+void
+gen7_upload_urb(intel_screen_private *intel)
+{
+ OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
+ OUT_BATCH(8); /* in 1KBs */
+
+ OUT_BATCH(GEN7_3DSTATE_URB_VS | (2 - 2));
+ OUT_BATCH(
+ (32 << GEN7_URB_ENTRY_NUMBER_SHIFT) | /* at least 32 */
+ (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
+ (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+
+ OUT_BATCH(GEN7_3DSTATE_URB_GS | (2 - 2));
+ OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
+ (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+
+ OUT_BATCH(GEN7_3DSTATE_URB_HS | (2 - 2));
+ OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
+ (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+
+ OUT_BATCH(GEN7_3DSTATE_URB_DS | (2 - 2));
+ OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
+ (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+}
+
+void
+gen6_upload_cc_state_pointers(intel_screen_private *intel,
+ drm_intel_bo *blend_bo,
+ drm_intel_bo *cc_bo,
+ drm_intel_bo *depth_stencil_bo)
+{
+ OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
+ if (blend_bo)
+ OUT_RELOC(blend_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+ else
+ OUT_BATCH(0);
+
+ if (depth_stencil_bo)
+ OUT_RELOC(depth_stencil_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+ else
+ OUT_BATCH(0);
+
+ if (cc_bo)
+ OUT_RELOC(cc_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+ else
+ OUT_BATCH(0);
+}
+
+void
+gen7_upload_cc_state_pointers(intel_screen_private *intel,
+ drm_intel_bo *blend_bo,
+ drm_intel_bo *cc_bo,
+ drm_intel_bo *depth_stencil_bo)
+{
+ OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
+ if (blend_bo)
+ OUT_RELOC(blend_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+ else
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2));
+ if (cc_bo)
+ OUT_RELOC(cc_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+ else
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS | (2 - 2));
+ if (depth_stencil_bo)
+ OUT_RELOC(depth_stencil_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+ else
+ OUT_BATCH(0);
+}
+
+void
+gen6_upload_sampler_state_pointers(intel_screen_private *intel,
+ drm_intel_bo *sampler_bo)
+{
+ OUT_BATCH(GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
+ GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
+ (4 - 2));
+ OUT_BATCH(0); /* VS */
+ OUT_BATCH(0); /* GS */
+ OUT_RELOC(sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+}
+
+void
+gen7_upload_sampler_state_pointers(intel_screen_private *intel,
+ drm_intel_bo *sampler_bo)
+{
+ OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
+ OUT_RELOC(sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+}
+
+void
+gen7_upload_bypass_states(intel_screen_private *intel)
+{
+ /* bypass GS */
+ OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
+ OUT_BATCH(0); /* without GS kernel */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* pass-through */
+
+ OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2));
+ OUT_BATCH(0);
+
+ /* disable HS */
+ OUT_BATCH(GEN7_3DSTATE_CONSTANT_HS | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN7_3DSTATE_HS | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2));
+ OUT_BATCH(0);
+
+ /* Disable TE */
+ OUT_BATCH(GEN7_3DSTATE_TE | (4 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ /* Disable DS */
+ OUT_BATCH(GEN7_3DSTATE_CONSTANT_DS | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN7_3DSTATE_DS | (6 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2));
+ OUT_BATCH(0);
+
+ /* Disable STREAMOUT */
+ OUT_BATCH(GEN7_3DSTATE_STREAMOUT | (3 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+}
+
+void
+gen6_upload_vs_state(intel_screen_private *intel)
+{
+ Bool ivb = INTEL_INFO(intel)->gen >= 70;
+ /* disable VS constant buffer */
+ OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | ((ivb ? 7 : 5) - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ if (ivb) {
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ }
+
+ OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2));
+ OUT_BATCH(0); /* without VS kernel */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* pass-through */
+}
+
+void
+gen6_upload_gs_state(intel_screen_private *intel)
+{
+ /* disable GS constant buffer */
+ OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
+ OUT_BATCH(0); /* without GS kernel */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* pass-through */
+}
+
+void
+gen6_upload_clip_state(intel_screen_private *intel)
+{
+ OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* pass-through */
+ OUT_BATCH(0);
+}
+
+void
+gen6_upload_sf_state(intel_screen_private *intel)
+{
+ OUT_BATCH(GEN6_3DSTATE_SF | (20 - 2));
+ OUT_BATCH((1 << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
+ (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
+ (0 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT));
+ OUT_BATCH(0);
+ OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
+ OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* DW9 */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* DW14 */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* DW19 */
+}
+
+void
+gen7_upload_sf_state(intel_screen_private *intel)
+{
+ OUT_BATCH(GEN7_3DSTATE_SBE | (14 - 2));
+ OUT_BATCH((1 << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
+ (1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) |
+ (0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* DW4 */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* DW9 */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN6_3DSTATE_SF | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
+ OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+}
+
+void
+gen6_upload_binding_table(intel_screen_private *intel,
+ uint32_t ps_binding_table_offset)
+{
+ /* Binding table pointers */
+ OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS |
+ GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS |
+ (4 - 2));
+ OUT_BATCH(0); /* VS */
+ OUT_BATCH(0); /* GS */
+ /* Only the PS uses the binding table */
+ OUT_BATCH(ps_binding_table_offset);
+}
+
+void
+gen7_upload_binding_table(intel_screen_private *intel,
+ uint32_t ps_binding_table_offset)
+{
+ OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
+ OUT_BATCH(ps_binding_table_offset);
+}
+
+void
+gen6_upload_depth_buffer_state(intel_screen_private *intel)
+{
+ OUT_BATCH(BRW_3DSTATE_DEPTH_BUFFER | (7 - 2));
+ OUT_BATCH((BRW_SURFACE_NULL << BRW_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT) |
+ (BRW_DEPTHFORMAT_D32_FLOAT << BRW_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(BRW_3DSTATE_CLEAR_PARAMS | (2 - 2));
+ OUT_BATCH(0);
+}
+
+void
+gen7_upload_depth_buffer_state(intel_screen_private *intel)
+{
+ OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
+ OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | (BRW_SURFACE_NULL << 29));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+}
diff --git a/src/i965_video.c b/src/i965_video.c
index 1054914..7d7ac79 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -1530,34 +1530,6 @@ gen6_create_vidoe_objects(ScrnInfoPtr scrn)
}
static void
-gen6_upload_invarient_states(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
- OUT_BATCH(BRW_PIPE_CONTROL_IS_FLUSH |
- BRW_PIPE_CONTROL_WC_FLUSH |
- BRW_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- BRW_PIPE_CONTROL_NOWRITE);
- OUT_BATCH(0); /* write address */
- OUT_BATCH(0); /* write data */
-
- OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
-
- OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
- OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
- GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
- OUT_BATCH(0);
-
- OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
- OUT_BATCH(1);
-
- /* Set system instruction pointer */
- OUT_BATCH(BRW_STATE_SIP | 0);
- OUT_BATCH(0);
-}
-
-static void
gen6_upload_state_base_address(ScrnInfoPtr scrn, drm_intel_bo *surface_state_binding_table_bo)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
@@ -1575,88 +1547,6 @@ gen6_upload_state_base_address(ScrnInfoPtr scrn, drm_intel_bo *surface_state_bin
}
static void
-gen6_upload_viewport_state_pointers(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- OUT_BATCH(GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
- GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
- (4 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_RELOC(intel->video.gen4_cc_vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
-}
-
-static void
-gen6_upload_urb(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- OUT_BATCH(GEN6_3DSTATE_URB | (3 - 2));
- OUT_BATCH(((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) |
- (24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
- OUT_BATCH((0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) |
- (0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */
-}
-
-static void
-gen6_upload_cc_state_pointers(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
- OUT_RELOC(intel->video.gen6_blend_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
- OUT_RELOC(intel->video.gen6_depth_stencil_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
- OUT_RELOC(intel->video.gen4_cc_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
-}
-
-static void
-gen6_upload_sampler_state_pointers(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- OUT_BATCH(GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
- GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
- (4 - 2));
- OUT_BATCH(0); /* VS */
- OUT_BATCH(0); /* GS */
- OUT_RELOC(intel->video.gen4_sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
-}
-
-static void
-gen6_upload_binding_table(ScrnInfoPtr scrn, uint32_t ps_binding_table_offset)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- /* Binding table pointers */
- OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS |
- GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS |
- (4 - 2));
- OUT_BATCH(0); /* vs */
- OUT_BATCH(0); /* gs */
- /* Only the PS uses the binding table */
- OUT_BATCH(ps_binding_table_offset);
-}
-
-static void
-gen6_upload_depth_buffer_state(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- OUT_BATCH(BRW_3DSTATE_DEPTH_BUFFER | (7 - 2));
- OUT_BATCH((BRW_SURFACE_NULL << BRW_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT) |
- (BRW_DEPTHFORMAT_D32_FLOAT << BRW_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- OUT_BATCH(BRW_3DSTATE_CLEAR_PARAMS | (2 - 2));
- OUT_BATCH(0);
-}
-
-static void
gen6_upload_drawing_rectangle(ScrnInfoPtr scrn, PixmapPtr pixmap)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
@@ -1668,87 +1558,6 @@ gen6_upload_drawing_rectangle(ScrnInfoPtr scrn, PixmapPtr pixmap)
}
static void
-gen6_upload_vs_state(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- /* disable VS constant buffer */
- OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | (5 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2));
- OUT_BATCH(0); /* without VS kernel */
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0); /* pass-through */
-}
-
-static void
-gen6_upload_gs_state(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- /* disable GS constant buffer */
- OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
- OUT_BATCH(0); /* without GS kernel */
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0); /* pass-through */
-}
-
-static void
-gen6_upload_clip_state(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0); /* pass-through */
- OUT_BATCH(0);
-}
-
-static void
-gen6_upload_sf_state(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- OUT_BATCH(GEN6_3DSTATE_SF | (20 - 2));
- OUT_BATCH((1 << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
- (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
- (0 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT));
- OUT_BATCH(0);
- OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
- OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0); /* DW9 */
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0); /* DW14 */
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0); /* DW19 */
-}
-
-static void
gen6_upload_wm_state(ScrnInfoPtr scrn, Bool is_packed)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
@@ -1857,262 +1666,25 @@ gen6_emit_video_setup(ScrnInfoPtr scrn,
IntelEmitInvarientState(scrn);
intel->last_3d = LAST_3D_VIDEO;
- gen6_upload_invarient_states(scrn);
+ gen6_upload_invariant_states(intel);
gen6_upload_state_base_address(scrn, surface_state_binding_table_bo);
- gen6_upload_viewport_state_pointers(scrn);
- gen6_upload_urb(scrn);
- gen6_upload_cc_state_pointers(scrn);
- gen6_upload_sampler_state_pointers(scrn);
- gen6_upload_vs_state(scrn);
- gen6_upload_gs_state(scrn);
- gen6_upload_clip_state(scrn);
- gen6_upload_sf_state(scrn);
+ gen6_upload_viewport_state_pointers(intel, intel->video.gen4_cc_vp_bo);
+ gen6_upload_urb(intel);
+ gen6_upload_cc_state_pointers(intel, intel->video.gen6_blend_bo, intel->video.gen4_cc_bo, intel->video.gen6_depth_stencil_bo);
+ gen6_upload_sampler_state_pointers(intel, intel->video.gen4_sampler_bo);
+ gen6_upload_vs_state(intel);
+ gen6_upload_gs_state(intel);
+ gen6_upload_clip_state(intel);
+ gen6_upload_sf_state(intel);
gen6_upload_wm_state(scrn, n_src_surf == 1 ? TRUE : FALSE);
- gen6_upload_binding_table(scrn, (n_src_surf + 1) * SURFACE_STATE_PADDED_SIZE);
- gen6_upload_depth_buffer_state(scrn);
+ gen6_upload_binding_table(intel, (n_src_surf + 1) * SURFACE_STATE_PADDED_SIZE);
+ gen6_upload_depth_buffer_state(intel);
gen6_upload_drawing_rectangle(scrn, pixmap);
gen6_upload_vertex_element_state(scrn);
gen6_upload_vertex_buffer(scrn, vertex_bo, end_address_offset);
gen6_upload_primitive(scrn);
}
-static void
-gen7_upload_invarient_states(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
- OUT_BATCH(BRW_PIPE_CONTROL_IS_FLUSH |
- BRW_PIPE_CONTROL_WC_FLUSH |
- BRW_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- BRW_PIPE_CONTROL_NOWRITE);
- OUT_BATCH(0); /* write address */
- OUT_BATCH(0); /* write data */
-
- OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
-
- OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (4 - 2));
- OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
- GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
- OUT_BATCH(1);
-
- /* Set system instruction pointer */
- OUT_BATCH(BRW_STATE_SIP | 0);
- OUT_BATCH(0);
-}
-
-static void
-gen7_upload_viewport_state_pointers(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
- OUT_RELOC(intel->video.gen4_cc_vp_bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0);
-
- OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
- OUT_BATCH(0);
-}
-
-/*
- * URB layout for Xv on GEN7
- * ----------------------------------------
- * | PS Push Constants (8KB) | VS entries |
- * ----------------------------------------
- */
-static void
-gen7_upload_urb(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
- OUT_BATCH(8); /* in 1KBs */
-
- OUT_BATCH(GEN7_3DSTATE_URB_VS | (2 - 2));
- OUT_BATCH(
- (32 << GEN7_URB_ENTRY_NUMBER_SHIFT) | /* at least 32 */
- (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
- (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
-
- OUT_BATCH(GEN7_3DSTATE_URB_GS | (2 - 2));
- OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
- (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
-
- OUT_BATCH(GEN7_3DSTATE_URB_HS | (2 - 2));
- OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
- (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
-
- OUT_BATCH(GEN7_3DSTATE_URB_DS | (2 - 2));
- OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
- (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
-}
-
-static void
-gen7_upload_cc_state_pointers(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2));
- OUT_RELOC(intel->video.gen4_cc_bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 1);
-
- OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
- OUT_RELOC(intel->video.gen6_blend_bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 1);
-
- OUT_BATCH(GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS | (2 - 2));
- OUT_RELOC(intel->video.gen6_depth_stencil_bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 1);
-}
-
-static void
-gen7_upload_sampler_state_pointers(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
- OUT_RELOC(intel->video.gen4_sampler_bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0);
-}
-
-static void
-gen7_upload_bypass_states(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- /* bypass GS */
- OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (7 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
- OUT_BATCH(0); /* without GS kernel */
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0); /* pass-through */
-
- OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2));
- OUT_BATCH(0);
-
- /* disable HS */
- OUT_BATCH(GEN7_3DSTATE_CONSTANT_HS | (7 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- OUT_BATCH(GEN7_3DSTATE_HS | (7 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2));
- OUT_BATCH(0);
-
- /* Disable TE */
- OUT_BATCH(GEN7_3DSTATE_TE | (4 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- /* Disable DS */
- OUT_BATCH(GEN7_3DSTATE_CONSTANT_DS | (7 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- OUT_BATCH(GEN7_3DSTATE_DS | (6 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2));
- OUT_BATCH(0);
-
- /* Disable STREAMOUT */
- OUT_BATCH(GEN7_3DSTATE_STREAMOUT | (3 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
-}
-
-static void
-gen7_upload_vs_state(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- /* disable VS constant buffer */
- OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | (7 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2));
- OUT_BATCH(0); /* without VS kernel */
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0); /* pass-through */
-}
-
-static void
-gen7_upload_sf_state(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- OUT_BATCH(GEN7_3DSTATE_SBE | (14 - 2));
- OUT_BATCH((1 << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
- (1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) |
- (0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0); /* DW4 */
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0); /* DW9 */
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- OUT_BATCH(GEN6_3DSTATE_SF | (7 - 2));
- OUT_BATCH(0);
- OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
- OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-}
-
static void
gen7_upload_wm_state(ScrnInfoPtr scrn, Bool is_packed)
{
@@ -2159,34 +1731,6 @@ gen7_upload_wm_state(ScrnInfoPtr scrn, Bool is_packed)
OUT_BATCH(0); /* kernel 2 pointer */
}
-static void
-gen7_upload_binding_table(ScrnInfoPtr scrn, uint32_t ps_binding_table_offset)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
- OUT_BATCH(ps_binding_table_offset);
-}
-
-static void
-gen7_upload_depth_buffer_state(ScrnInfoPtr scrn)
-{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
- OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
- (BRW_SURFACE_NULL << 29));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
-}
-
static void
gen7_upload_vertex_buffer(ScrnInfoPtr scrn, drm_intel_bo *vertex_bo, uint32_t end_address_offset)
{
@@ -2231,19 +1775,19 @@ gen7_emit_video_setup(ScrnInfoPtr scrn,
IntelEmitInvarientState(scrn);
intel->last_3d = LAST_3D_VIDEO;
- gen7_upload_invarient_states(scrn);
+ gen6_upload_invariant_states(intel);
gen6_upload_state_base_address(scrn, surface_state_binding_table_bo);
- gen7_upload_viewport_state_pointers(scrn);
- gen7_upload_urb(scrn);
- gen7_upload_cc_state_pointers(scrn);
- gen7_upload_sampler_state_pointers(scrn);
- gen7_upload_bypass_states(scrn);
- gen7_upload_vs_state(scrn);
- gen6_upload_clip_state(scrn);
- gen7_upload_sf_state(scrn);
+ gen7_upload_viewport_state_pointers(intel, intel->video.gen4_cc_vp_bo);
+ gen7_upload_urb(intel);
+ gen7_upload_cc_state_pointers(intel, intel->video.gen6_blend_bo, intel->video.gen4_cc_bo, intel->video.gen6_depth_stencil_bo);
+ gen7_upload_sampler_state_pointers(intel, intel->video.gen4_sampler_bo);
+ gen7_upload_bypass_states(intel);
+ gen6_upload_vs_state(intel);
+ gen6_upload_clip_state(intel);
+ gen7_upload_sf_state(intel);
gen7_upload_wm_state(scrn, n_src_surf == 1 ? TRUE : FALSE);
- gen7_upload_binding_table(scrn, (n_src_surf + 1) * SURFACE_STATE_PADDED_SIZE);
- gen7_upload_depth_buffer_state(scrn);
+ gen7_upload_binding_table(intel, (n_src_surf + 1) * SURFACE_STATE_PADDED_SIZE);
+ gen7_upload_depth_buffer_state(intel);
gen6_upload_drawing_rectangle(scrn, pixmap);
gen6_upload_vertex_element_state(scrn);
gen7_upload_vertex_buffer(scrn, vertex_bo, end_address_offset);
diff --git a/src/intel.h b/src/intel.h
index 6135349..3f48dd4 100644
--- a/src/intel.h
+++ b/src/intel.h
@@ -597,6 +597,35 @@ void i965_vertex_flush(intel_screen_private *intel);
void i965_batch_flush(intel_screen_private *intel);
void i965_batch_commit_notify(intel_screen_private *intel);
+/* i965_3d.c */
+void gen6_upload_invariant_states(intel_screen_private *intel);
+void gen6_upload_viewport_state_pointers(intel_screen_private *intel,
+ drm_intel_bo *cc_vp_bo);
+void gen7_upload_viewport_state_pointers(intel_screen_private *intel,
+ drm_intel_bo *cc_vp_bo);
+void gen6_upload_urb(intel_screen_private *intel);
+void gen7_upload_urb(intel_screen_private *intel);
+void gen6_upload_cc_state_pointers(intel_screen_private *intel,
+ drm_intel_bo *blend_bo, drm_intel_bo *cc_bo,
+ drm_intel_bo *depth_stencil_bo);
+void gen7_upload_cc_state_pointers(intel_screen_private *intel,
+ drm_intel_bo *blend_bo, drm_intel_bo *cc_bo,
+ drm_intel_bo *depth_stencil_bo);
+void gen6_upload_sampler_state_pointers(intel_screen_private *intel,
+ drm_intel_bo *sampler_bo);
+void gen7_upload_sampler_state_pointers(intel_screen_private *intel,
+ drm_intel_bo *sampler_bo);
+void gen7_upload_bypass_states(intel_screen_private *intel);
+void gen6_upload_gs_state(intel_screen_private *intel);
+void gen6_upload_vs_state(intel_screen_private *intel);
+void gen6_upload_clip_state(intel_screen_private *intel);
+void gen6_upload_sf_state(intel_screen_private *intel);
+void gen7_upload_sf_state(intel_screen_private *intel);
+void gen6_upload_binding_table(intel_screen_private *intel, uint32_t ps_binding_table_offset);
+void gen7_upload_binding_table(intel_screen_private *intel, uint32_t ps_binding_table_offset);
+void gen6_upload_depth_buffer_state(intel_screen_private *intel);
+void gen7_upload_depth_buffer_state(intel_screen_private *intel);
+
Bool intel_transform_is_affine(PictTransformPtr t);
Bool
intel_get_transformed_coordinates(int x, int y, PictTransformPtr transform,
--
1.7.4.4
More information about the Intel-gfx
mailing list