[Intel-gfx] [PATCH 11/16] intel: Put urb and thread limits into the chipset struct

[Kristian Høgsberg]

---
 src/mesa/drivers/dri/i965/brw_context.c   |   53 ++++-------------------------
 src/mesa/drivers/dri/intel/intel_screen.c |   46 +++++++++++++++++++++----
 src/mesa/drivers/dri/intel/intel_screen.h |    7 ++++
 3 files changed, 53 insertions(+), 53 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index d6a99ab..e2263d5 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -177,53 +177,14 @@ GLboolean brwCreateContext( int api,
       brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_965;
    }
 
-   /* WM maximum threads is number of EUs times number of threads per EU. */
-   if (intel->gen >= 7) {
-      if (IS_IVB_GT1(intel->intelScreen->deviceID)) {
-	 brw->wm_max_threads = 86;
-	 brw->vs_max_threads = 36;
-	 brw->urb.size = 128;
-	 brw->urb.max_vs_entries = 512;
-	 brw->urb.max_gs_entries = 192;
-      } else if (IS_IVB_GT2(intel->intelScreen->deviceID)) {
-	 brw->wm_max_threads = 86;
-	 brw->vs_max_threads = 128;
-	 brw->urb.size = 256;
-	 brw->urb.max_vs_entries = 704;
-	 brw->urb.max_gs_entries = 320;
-      } else {
-	 assert(!"Unknown gen7 device.");
-      }
-   } else if (intel->gen == 6) {
-      if (IS_SNB_GT2(intel->intelScreen->deviceID)) {
-	 /* This could possibly be 80, but is supposed to require
-	  * disabling of WIZ hashing (bit 6 of GT_MODE, 0x20d0) and a
-	  * GPU reset to change.
-	  */
-	 brw->wm_max_threads = 40;
-	 brw->vs_max_threads = 60;
-	 brw->urb.size = 64;            /* volume 5c.5 section 5.1 */
-	 brw->urb.max_vs_entries = 256; /* volume 2a (see 3DSTATE_URB) */
-      } else {
-	 brw->wm_max_threads = 40;
-	 brw->vs_max_threads = 24;
-	 brw->urb.size = 32;            /* volume 5c.5 section 5.1 */
-	 brw->urb.max_vs_entries = 128; /* volume 2a (see 3DSTATE_URB) */
-      }
-   } else if (intel->gen == 5) {
-      brw->urb.size = 1024;
-      brw->vs_max_threads = 72;
-      brw->wm_max_threads = 12 * 6;
-   } else if (intel->is_g4x) {
-      brw->urb.size = 384;
-      brw->vs_max_threads = 32;
-      brw->wm_max_threads = 10 * 5;
-   } else if (intel->gen < 6) {
-      brw->urb.size = 256;
-      brw->vs_max_threads = 16;
-      brw->wm_max_threads = 8 * 4;
+   brw->wm_max_threads = intel->intelScreen->chipset.wm_max_threads;
+   brw->vs_max_threads = intel->intelScreen->chipset.vs_max_threads;
+   brw->urb.size = intel->intelScreen->chipset.urb_size;
+   brw->urb.max_vs_entries = intel->intelScreen->chipset.urb_max_vs_entries;
+   brw->urb.max_gs_entries = intel->intelScreen->chipset.urb_max_gs_entries;
+
+   if (intel->gen == 4)
       brw->has_negative_rhw_bug = GL_TRUE;
-   }
 
    if (INTEL_DEBUG & DEBUG_SINGLE_THREAD) {
       brw->vs_max_threads = 1;
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 86b4000..bb178e3 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -471,31 +471,63 @@ extern GLboolean i915CreateContext(int api,
 #else
 
 static const struct intel_chipset intel_chipset_i965 = {
-   .gen = 4
+   .gen = 4,
+   .urb_size = 256,
+   .vs_max_threads = 16,
+   .wm_max_threads = 8 * 4,
 };
 
 static const struct intel_chipset intel_chipset_g4x = {
-   .gen = 4
+   .gen = 4,
+   .urb_size = 384,
+   .vs_max_threads = 32,
+   .wm_max_threads = 10 * 5
 };
 
 static const struct intel_chipset intel_chipset_ilk = {
-   .gen = 5
+   .gen = 5,
+   .urb_size = 1024,
+   .vs_max_threads = 72,
+   .wm_max_threads = 12 * 6
 };
 
 static const struct intel_chipset intel_chipset_snb_gt1 = {
-   .gen = 6
+   .gen = 6,
+   .wm_max_threads = 40,
+   .vs_max_threads = 24,
+   .urb_size = 32,            /* volume 5c.5 section 5.1 */
+   .urb_max_vs_entries = 128  /* volume 2a (see 3DSTATE_URB) */
+
 };
 
 static const struct intel_chipset intel_chipset_snb_gt2 = {
-   .gen = 6
+   .gen = 6,
+   /* This could possibly be 80, but is supposed to require
+    * disabling of WIZ hashing (bit 6 of GT_MODE, 0x20d0) and a
+    * GPU reset to change.
+    */
+   .wm_max_threads = 40,
+   .vs_max_threads = 60,
+   .urb_size = 64,            /* volume 5c.5 section 5.1 */
+   .urb_max_vs_entries = 256  /* volume 2a (see 3DSTATE_URB) */
 };
 
 static const struct intel_chipset intel_chipset_ivb_gt1 = {
-   .gen = 7
+   .gen = 7,
+   .wm_max_threads = 86,
+   .vs_max_threads = 36,
+   .urb_size = 128,
+   .urb_max_vs_entries = 512,
+   .urb_max_gs_entries = 192
 };
 
 static const struct intel_chipset intel_chipset_ivb_gt2 = {
-   .gen = 7
+   .gen = 7,
+   .wm_max_threads = 86,
+   .vs_max_threads = 128,
+   .urb_size = 256,
+   .urb_max_vs_entries = 704,
+   .urb_max_gs_entries = 320
 };
 
 static const struct intel_chipset_map chipset_map[] = {
diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h
index bfcc20d..fba62e0 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.h
+++ b/src/mesa/drivers/dri/intel/intel_screen.h
@@ -37,6 +37,13 @@
 struct intel_chipset {
    int gen;
    GLboolean is_945; 
+
+   /* WM maximum threads is number of EUs times number of threads per EU. */
+   int wm_max_threads;
+   int vs_max_threads;
+   int urb_size;
+   int urb_max_vs_entries;
+   int urb_max_gs_entries;
 };
 
 struct intel_screen
-- 
1.7.4.4