[Intel-gfx] [PATCH 5/5] Xv: set up pipeline for Xv on Ivybridge

[Owain Ainsworth]

On Thu, Jun 23, 2011 at 12:47:47AM +0800, Xiang, Haihao wrote:
> The configuration is same as that on Sandybridge, but
> many state commands are changed
> 
> Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
> ---
>  src/i965_reg.h   |  132 ++++++++++++++++
>  src/i965_video.c |  446 +++++++++++++++++++++++++++++++++++++++++++++++++++---
>  2 files changed, 554 insertions(+), 24 deletions(-)
> 
> diff --git a/src/i965_reg.h b/src/i965_reg.h
> index df41fba..ab6c020 100644
> --- a/src/i965_reg.h
> +++ b/src/i965_reg.h
> --- a/src/i965_video.c
> +++ b/src/i965_video.c
> @@ -1445,6 +1445,7 @@ gen6_create_blend_state(ScrnInfoPtr scrn)
>  
>  	blend_state->blend1.logic_op_enable = 1;
>  	blend_state->blend1.logic_op_func = 0xc;
> +	blend_state->blend1.pre_blend_clamp_enable = 1;
>  
>  	drm_intel_bo_unmap(blend_bo);
>  	return blend_bo;

Can you please explain why this chunk is added for all gen6 and above?

-0-
-- 
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