[Intel-gfx] [PATCH 3/8] drm/i915: Flush the plane enable using the DSPCNTR latch

[Keith Packard]

This comment is misleading -- the patch replaces a call to
intel_wait_for_vblank with a call to intel_flush_display_plane.

From my reading of the docs, enable requires two actions:

 1) DSPACNTR with enable going from 0->1
 2) wait for vblank

At disable, three actions are required:

 1) DSPACNTR with enable going from 1->0
 2) DSPASURF(965+)/DSPAADDR(otherwise) write to trigger the register updates
 3) wait for vblank

-- 
keith.packard at intel.com
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