[Intel-gfx] Pipelined fence fixes

[Chris Wilson]

Spurred on by the tiling corruption caused by "disabling" the pipelined
fencing, I think I finally fixed the GPU hangs plaguing the
implementation. (It's a matter of timing and making sure that is
sufficient serialisation between the CPU and GPU writes to the fence
registers, but not too much...)

This is quite hairy code, but is required to fix the stalls introduced
to prevent the tiling corruption.
-Chris