[Intel-gfx] [PATCH 5/8] drm/i915: save/restore MI_ARB_STATE only for gen3

[Jesse Barnes]

On Mon, 21 Mar 2011 17:27:16 +0800
Zhenyu Wang <zhenyuw at linux.intel.com> wrote:

> Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_suspend.c |    6 ++++--
>  1 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index 11e61a3..26387c3 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -820,7 +820,8 @@ int i915_save_state(struct drm_device *dev)
>  		gen6_disable_rps(dev);
>  
>  	/* Memory Arbitration state */
> -	dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
> +	if (IS_GEN3(dev))
> +		dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
>  
>  	/* Scratch space */
>  	for (i = 0; i < 16; i++) {
> @@ -865,7 +866,8 @@ int i915_restore_state(struct drm_device *dev)
>  		gen6_enable_rps(dev_priv);
>  
>  	/* Memory arbitration state */
> -	I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
> +	if (IS_GEN3(dev))
> +		I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
>  
>  	for (i = 0; i < 16; i++) {
>  		I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);

This register exists on gen4 as well, though as with CACHE_MODE_0, we
should probably be setting it to a good value rather than simply
trusting the BIOS.

-- 
Jesse Barnes, Intel Open Source Technology Center