[Intel-gfx] [PATCH 4/4] drm/i915: move sandybridge RC6 enable in resume after ring initialization

[Zhenyu Wang]

Move RC6 enable after we reset rings for all regines, if e.g render ring
is disabled when RC6 enable on Sandybridge, hw won't save render context
image if any chance when enter RC6. Also match the order like we do in
driver load.

Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c     |    3 +++
 drivers/gpu/drm/i915/i915_suspend.c |    3 ---
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 22ec066..e675ba9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -378,6 +378,9 @@ static int i915_drm_thaw(struct drm_device *dev)
 
 		if (IS_IRONLAKE_M(dev))
 			ironlake_enable_rc6(dev);
+
+		if (IS_GEN6(dev))
+			gen6_enable_rps(dev_priv);
 	}
 
 	intel_opregion_init(dev);
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index bce24d8..08c1d04 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -875,9 +875,6 @@ int i915_restore_state(struct drm_device *dev)
 		intel_init_emon(dev);
 	}
 
-	if (IS_GEN6(dev))
-		gen6_enable_rps(dev_priv);
-
 	/* Cache mode state */
 	I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
 
-- 
1.7.4.1